View GE28F256K3C120_7768184.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

intel strataflash ? synchronous memory (k3/k18) 28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 (x16) datasheet product features the intel strataflash ? synchronous memory (k3/k18) product line adds a high performance burst-mode interface and other additional features to the intel strataflash ? memory family of products. just like its j3 counterpart, the k3/k18 device utilizes reliable and proven two-bit-per- cell technology to deliver 2x the memory in 1x the space, offering high density flash at low cost. this is intel?s third generation mlc technology, manufactured on 0.18 m lithography, making it the most widely used and proven mlc product family on the market. k3/k18 is a 3-volt device (core), but it is available with 3-volt (k3) or 1.8-volt (k18) i/o voltages. these devices are ideal for mainstream applications requiring large storage space for both code and data storage. advanced system designs will benefit from the high performance page and burst modes for direct execution from the flash memory. available in densities from 64 mbit to 256 mbit (32 mbyte), the k3/k18 device is the highest density nor-based flash component available today, just as it was when intel introduced the original device in 1997. performance ? 110/115/120 ns initial access speed for 64/128/256 mbit densities ? 25 ns asynchronous page-mode reads, 8 words wide ? 13 ns synchronous burst-mode reads, 8 or 16 words wide ? 32-word write buffer ? buffered enhanced factory programming software ? 25 s (typ.) program and erase suspend latency time ? flash data integrator (fdi), common flash interface (cfi) compatible ? programmable wait signal polarity quality and reliability ? operating temperature: ?40 c to +85 c ? 100k minimum erase cycles per block ? 0.18 m etox? vii process architecture ? multi-level cell technology: high density at low cost ? symmetrical 64 k-word blocks ? 256 mbit (256 blocks) ? 128 mbit (128 blocks) ? 64 mbit (64 blocks) ?ideal for ?code + data? applications security ? 2-kbit protection register ? unique 64-bit device identifier ? absolute data protection with v pen and wp# ? individual and instantaneous block locking, unlocking and lock-down capability packaging and voltage ?64-ball intel ? easy bga package (128-mbit is also offered in a lead-free package) ? 56-and 79-ball intel ? vf bga package ?v cc = 2.70 v to 3.60 v ?v ccq = 1.65 to 1.95 v/2.375 to 3.60 v order number: 290737-009 february 2005 notice: this document contains information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the lat- est datasheet before finalizing a design.
2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 3 volt synchronous intel strataflash ? memory may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2005. *other names and brands may be claimed as the property of others.
datasheet 3 28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 contents 1.0 introduction ..................................................................................................................7 1.1 nomenclature ........................................................................................................7 1.2 conventions ..........................................................................................................8 2.0 functional overview .................................................................................................9 2.1 high performance page/burst modes...................................................................9 2.2 single chip solution ..............................................................................................9 2.3 packaging options ..............................................................................................10 2.4 product highlights ...............................................................................................10 2.5 k3/k18 block diagram ........................................................................................11 2.6 memory map .......................................................................................................12 3.0 package information ...............................................................................................13 3.1 easy bga package.............................................................................................13 3.2 vf bga for 64 mbit and 128 mbit package ........................................................14 3.3 vf bga for 256 mbit package ............................................................................15 4.0 ballout and signal description ...........................................................................17 4.1 64-ball easy bga package for all densities (1.0 mm ball pitch) .......................17 4.2 56-ball vf bga package for 64- and 128-mbit density (0.75 mm ball pitch) ....18 4.3 79-ball vf bga for 256-mbit density package...................................................19 4.4 signal descriptions..............................................................................................20 5.0 maximum ratings and operating conditions ..............................................21 5.1 absolute maximum ratings.................................................................................21 5.2 operating conditions...........................................................................................21 6.0 electrical specifications ........................................................................................22 6.1 dc current characteristics .................................................................................22 7.0 ac characteristics ...................................................................................................24 7.1 read operations .................................................................................................24 7.2 write operation ...................................................................................................29 7.3 block erase and program operation performance .............................................31 7.4 ac test conditions .............................................................................................32 7.5 capacitance ........................................................................................................32 8.0 power and reset .......................................................................................................33 8.1 power-up/down characteristics .........................................................................33 8.2 power supply decoupling ...................................................................................33 8.3 reset characteristics ..........................................................................................33 8.4 reset operation ..................................................................................................34 9.0 bus operations .........................................................................................................35 9.1 bus operations overview....................................................................................35 9.1.1 read mode.............................................................................................35 9.1.2 write/program ........................................................................................36
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 4 datasheet 9.1.3 output disable ....................................................................................... 36 9.1.4 standby .................................................................................................. 36 9.1.5 reset ...................................................................................................... 36 9.2 device commands .............................................................................................. 37 10.0 read modes ................................................................................................................ 39 10.1 asynchronous page-mode read ........................................................................ 39 10.2 synchronous burst-mode read .......................................................................... 40 10.3 read configuration register ............................................................................... 40 10.3.1 read mode............................................................................................. 41 10.3.2 latency count ........................................................................................ 41 10.3.3 wait polarity ......................................................................................... 43 10.3.4 data hold ............................................................................................... 43 10.3.5 wait delay ............................................................................................ 44 10.3.6 burst sequence...................................................................................... 44 10.3.7 clock edge ............................................................................................. 44 10.3.8 burst length ........................................................................................... 44 11.0 program modes ......................................................................................................... 45 11.1 word programming ............................................................................................. 45 11.2 write-buffer programming .................................................................................. 45 11.3 program suspend ............................................................................................... 46 11.4 program resume ................................................................................................ 47 11.5 buffered enhanced factory programming (buffered-efp)................................. 47 11.5.1 buffered-efp requirements and considerations .................................. 47 11.5.2 buffered-efp setup phase .................................................................... 48 11.5.3 buffered-efp program and verify phase .............................................. 48 11.5.4 buffered-efp exit phase ....................................................................... 49 12.0 erase mode ................................................................................................................. 50 12.1 block erase ......................................................................................................... 50 12.2 erase suspend.................................................................................................... 50 12.3 erase resume .................................................................................................... 51 13.0 security modes ......................................................................................................... 52 13.1 block locking operations ................................................................................... 52 13.1.1 block lock .............................................................................................. 53 13.1.2 block unlock .......................................................................................... 53 13.1.3 block lock-down ................................................................................... 53 13.1.4 block lock during erase suspend......................................................... 53 13.1.5 wp# lock-down control ........................................................................ 53 13.2 protection registers ............................................................................................ 54 13.2.1 reading the protection registers .......................................................... 55 13.2.2 programming the protection registers .................................................. 55 13.2.3 locking the protection registers ........................................................... 55 13.3 array protection .................................................................................................. 55 14.0 special modes ........................................................................................................... 56 14.1 read status register .......................................................................................... 56 14.1.1 clear status register ............................................................................. 57 14.2 read device identifier ......................................................................................... 57
datasheet 5 28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 14.3 read query/cfi ..................................................................................................58 14.4 sts configuration (easy bga package only)..................................................58 appendix a write state machine (wsm) .............................................................................. 59 appendix b common flash interface ................................................................................... 64 appendix c flowcharts ............................................................................................................... 70 appendix d additional information ....................................................................................... 78 appendix e ordering information .......................................................................................... 79
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 6 datasheet revision history date of revision revision description 08/22/01 -001 original version 09/24/01 -002 corrected typographical errors in 11.0 ac characteristics section. 09/27/01 -003 change vfbga package from 64 to 56 ball package. add ordering info in appendix e. 02/22/02 -004 changes to ballouts per engineering review and editing/formatting updates. 06/17/02 -005 changes to iccr, elimination of speed bin 2, expansion of vccq range. 06/11/03 -006 corrections to ordering information, typcs, added next-state table, appendix a info. added table of latency count settings to section 4.3.2. 12/01/03 -007 update pdf presentation. 5/19/04 -008 reformatted the document layout. 2/1/05 -009 added lead-free information.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 7 1.0 introduction this document contains information pertaining to the intel strataflash ? synchronous memory (k3/k18) device. the purpose of this document is to describe the features, operations and specifications of these devices. 1.1 nomenclature 3 volt core: v cc range of 2.7 v ? 3.6 v 3 volt i/o: v ccq range of 2.375 v ? 3.6 v 1.8 volt i/o: v ccq range of 1.65 v ? 1.95 v a min : for easy bga packages: a min = a1 for vf bga packages: a min = a0 a max : for easy bga packages: 64 mbit a max = a22 128 mbit a max = a23 256 mbit a max = a24 for vf bga packages: 64 mbit a max = a21 128 mbit a max = a22 256 mbit a max = a23 block: a group of flash cells that share common erase circuitry and erase simultaneously program: to write data to the flash array vpen: refers to a signal or package connection name v pen : refers to timing or voltage levels cui: command user interface otp: one time programmable pr: protection register plr: protection lock register rfu: reserved for future use sr: status register rcr: read configuration register wsm: write state machine mlc: multi-level cell set: indicates a logic one (1) clear: indicates a logic zero (0)
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 8 datasheet 1.2 conventions 0x: hexadecimal prefix 0b: binary prefix k (noun): 1,000 m (noun): 1,000,000 byte: 8 bits word: 16 bits kword: 1,024 words kb: 1,024 bits kb: 1,024 bytes mb: 1,048,576 bits mb: 1,048,576 bytes brackets: square brackets ([]) will be used to designate group membership or to define a group of signals with similar function (i.e. a[21:1], sr[4,1] and d[15:0]).
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 9 2.0 functional overview this section provides an overview of the k3/k18 device features and architecture. the k3/k18 device product line adds a high performance burst-mode interface and other additional features to the intel strataflash ? memory family of products. just like its j3 counterpart, the k3/k18 utilizes reliable and proven two-bit-pe r-cell technology to deliver 2x the memory in 1x the space, offering high density flash at low cost. this is the third generation of intel's multi-level cell (mlc) technology, manufactured on 0.18 m lithography, making it the most widely used and proven mlc product family on the market. k3/k18 is a 3-volt device (core), but it is available with 3-volt (k3) or 1.8-volt (k18) i/o voltages. these devices are ideal for mainstream applications requiring large storage space for both code and data storage. advanced system designs will benefit from the high performance page and burst modes for direct execution from the flash memory. available in densities from 64 mb to 256 mbit (32 mbyte), the k3/k18 device is the highest density nor-based flash component available today, just as it was when intel introduced the original device in 1997. 2.1 high performance page/burst modes nor-based flash is generally preferred over other architectures for its reliability and fast read speeds. fast reads allow the application to execute code directly out of flash, rather than downloading to ram for execution, saving the costs of redundant system memory and board space. the k3/k18 device sets the standard for fast read speeds by adding burst mode and utilizing an 8 word page mode. burst mode increases throughput up to 76mb/s, effectively five times faster than asynchronous reads on standard flash memory, and supports performance up to 66 mhz with zero wait states. both page and burst modes also provide a high performance glueless interface to the intel ? strongarm* sa-1110 cpu (and future intel ? xscale processors) and many other microprocessors. 2.2 single chip solution in addition to code execution, many applications also have data storage needs. k3/k18 memory provides a single-chip solution for combined code execution and data storage. a single-chip solution is easy to implement by utilizing a unique hardware and software combination: the k3/ k18 device and intel ? persistent storage manager (intel ? psm). intel ? psm is royalty free when used with intel ? flash, is an installable file system and block device driver for microsoft windows* ce os version 2.1 and later. the intel ? psm software is appropriate for any application using the microsoft windows ce operating system, including pc companions, set-top boxes, and other connected appliances and hand-held devices. other operating system ports are also available. intel ? psm is optimized for the intel strataflash ? memory product line. for wireless applications, intel ? flash data integrator (intel ? fdi) version 4 software provides the ability to manage data and files in intel strataflash ? memory in an open architecture, including support for downloaded java* applets, bluetooth* file transfers, and voice recognition tags.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 10 datasheet 2.3 packaging options the k3/k18 device is available in multiple packages: lead and lead-free easy bga and vf bga, and stacked chip scale package (scsp, stacking with sram or flash + flash). the 64-ball easy bga package provides sop reliability and long-term footprint compatibility and cost in a chip scale package size. the vf bga and scsp offer small footprints for wireless applications. manufactured on the intel 0.18-micron process technology, intel strataflash ? memory offers unprecedented value and performance and reliability. 2.4 product highlights high performance read modes: 8 or 16-word synchronous burst, 8-word page: ? 64 mb: 110/25/13 ns (async/page/burst) ? 128 mb: 115/25/13 ns (offered in both lead and lead-free easy bga packages) ? 256 mb:120/25/13 ns ? 2.7 v to 3.6 v vcc operation ? 64-ball easy bga ? vf bga packages and stacked chip scale package (scsp) ? i/o v ccq : 2.375 v to 3.6 v (k3); 1.65 v to 1.95 v (k18) ? one-time-programmable protection registers (2kbits) ? program and erase suspend capability ? cost-effective multi-level cell architecture ? royalty-free software support for most applications with intel ? psm, intel ? fdi version 4, or vfm ? full extended operating temperature: -40 c to +85 c ? proven reliability: 100,000 cycles, up to 20 years data retention
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 11 2.5 k3/k18 block diagram figure 1. k3/k18 device memory block diagram 64-mbit: sixty-four 128-mbit: one-hundred twenty-eight 256-mbit two-hundred fifty-six 64kword blocks input buffer output multiplexer y-gating program/erase voltage switch data comparator status register identifier register data register i/o logic address latch address counter x-decoder y-decoder input buffer output buffer gnd v ccq v pen ce# we# oe# rst# command user interface dq 0 - dq 15 v cc write buffer write state machine input multiplexer query sts v ccq read state machine v ccq clk adv# wait amax : amin
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 12 datasheet 2.6 memory map the k3/k18 device array is divided into symmetrical blocks that are 64-kword in size. a 64 mbit device contains 64 blocks, a 128 mbit device contains 128 blocks and a 256 mbit device contains 256 blocks. flash cells within a block are organized by rows and columns. a block contains 512 rows by 128 words. the words on a row are divided into 16 eight-word groups. (see figure 2 .) figure 2. k3/k18 device memory map block 0 block 1 block 2 block 3 . . . block 63 . . . block 127 . . . block 255 256-mbit device 128-mbit device 64-mbit device 0xffff 0x3fffff 0x1ffff 0x2ffff 0x3ffff 0x7fffff 0xffffff 0 0x3f0000 0x7f0000 0xff0000
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 13 3.0 package information 3.1 easy bga package figure 3. easy bga package drawing table 1. easy bga package dimensions (sheet 1 of 2) millimeters inches symbol min nom max notes min nom max package height a 1.200 0.0472 ball height a1 0.250 0.0098 package body thickness a2 0.780 0.0307 ball width b 0.330 0.430 0.530 0.0130 0.0169 0.0209 package body width (64 mb, 128 mb, 256 mb) d 9.900 10.000 10.100 1 0.3898 0.3937 0.3976 package body length (64 mb, 128 mb) e 12.900 13.000 13.100 1 0.5079 0.5118 0.5157 package body length (256 mb) e 14.900 15.000 15.100 1 0.5866 0.5906 0.5945 pitch [e] 1.000 0.0394 ball count n 64 64 e seating plane s1 s2 e top view - ball side down bottom view - ball side up y a a1 d ball a1 corner a2 note: drawing not to scale a b c d e f g h 87654321 8 7 6 5 4 3 2 1 a b c d e f g h b ball a1 corner
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 14 datasheet 3.2 vf bga for 64 mbit and 128 mbit package seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d (64/128/256 mb) s1 1.400 1.500 1.600 1 0.0551 0.0591 0.0630 corner to ball a1 distance along e (64/128 mb) s2 2.900 3.000 3.100 1 0.1142 0.1181 0.1220 corner to ball a1 distance along e (256 mb) s2 3.900 4.000 4.100 1 0.1535 0.1575 0.1614 figure 4. vf bga for 64 mb and 128 mb package drawing table 2. vf bga package (64 mb and 128 mb) dimensions (sheet 1 of 2) millimeters inches symbol min nom max notes min nom max package height a 1.000 0.0394 ball height a1 0.150 0.0059 package body thickness a2 0.665 0.0262 table 1. easy bga package dimensions (sheet 2 of 2) millimeters inches symbol min nom max notes min nom max seating plane y a a1 a2 e note: drawing not to scale ball a1 corner a b c d e f g 8 7 6 5 4 3 2 1 e top view - bump side down d bottom view - ball side up ball a1 corner s 1 b 876 54321 a b c d e f g 2 s
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 15 3.3 vf bga for 256 mbit package ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body width (64 mb) d 7.600 7.700 7.800 1 0.2992 0.3031 0.3071 package body width (128 mb) d 10.900 11.000 11.100 1 0.4291 0.4331 0.4370 package body length (64 mb, 128 mb) e 8.900 9.000 9.100 1 0.3504 0.3543 0.3583 pitch [e] 0.750 0.0295 ball (lead) count n 56 56 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d (64 mb) s1 1.125 1.225 1.325 1 0.0443 0.0482 0.0522 corner to ball a1 distance along e (128 mb) s1 2.775 2.875 2.975 1 0.1093 0.1132 0.1171 corner to ball a1 distance along e (64 mb, 128 mb) s2 2.150 2.250 2.350 1 0.0846 0.0886 0.0925 figure 5. vf bga package 256 mb drawing table 2. vf bga package (64 mb and 128 mb) dimensions (sheet 2 of 2) millimeters inches symbol min nom max notes min nom max bottom view - bump side up top view - bump side down pin # 1 indicator e d a b c d e f 678 5 4 3 2 1 g side view a 2 a seating plan y a 1 9 11 12 13 10 f note: drawing not to scale b 6 7 8 5 4321 9 11 12 13 10 a b c d e g e pin # 1 corner s 1 s 2
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 16 datasheet table 3. vf bga (256 mb) dimensions millimeters inches symbol min nom max notes min nom max package height a 1.000 0.0394 ball height a1 0.150 0.0059 package body thickness a2 0.665 0.0262 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body width d 14.400 14.500 14.600 1 0.5669 0.5709 0.5748 package body length e 8.900 9.000 9.100 1 0.3504 0.3543 0.3583 pitch [e] 0.750 0.0295 ball (lead) count n 79 79 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d s1 2.650 2.750 2.850 1 0.1043 0.1083 0.1122 corner to ball a1 distance along e s2 2.150 2.250 2.350 1 0.0846 0.0886 0.0925
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 17 4.0 ballout and signal description the k3/k18 device is available in a 64-ball easy bga package for the 64-, 128-, and 256 mbit densities. see figure 6 . this device is also available in a 56-ball vf bga package for the 64- and 128-mbit densities and a 79-ball vf bga package for the 256-mbit density. see figure 7 on page 18 and figure 8 on page 19 . 4.1 64-ball easy bga package for all densities (1.0 mm ball pitch) figure 6. 64-ball easy bga package for all available densities (1.0 mm ball pitch) notes: 1. address a23 is valid only on 128-mbit densities and above; otherwise, it is a no connect (nc). 2. address a24 is valid only on 256-mbit density; otherwise, it is a no connect (nc). 18 23 45 6 7 a a1 a6 a8 a13 vpen a18 a22 vcc rfu vssq vcc d13 vss d7 a24 256m vssq h a23 128m rfu d2 d5 vccq d14 we# d6 g rfu d0 d10 d12 d11 wait oe# adv# f e d8 d1 d9 d4 d3 d15 sts clk d a4 a5 a11 vccq rst# a16 a17 vccq c a3 a7 a10 a15 a12 a20 a21 wp# b a2 vss a9 a14 ce# a19 rfu rfu 1 8 2 3 4 5 6 7 rfu vssq vcc d13 vss d7 a24 256m vssq h we# g rfu oe# f e sts d a4 a5 a11 vccq rst# a16 a17 vccq c a3 a7 a10 a15 a12 a20 a21 wp# b a2 vss a9 a14 ce# a19 rfu rfu a a1 a6 a8 a13 vpen a18 a22 vcc top view - ball side down bottom view - ball sideup version -easy bga version - easy bga a23 128m rfu d2 d5 vccq d14 d6 d0 d10 d12 d11 wait adv# d8 d1 d9 d4 d3 d15 clk
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 18 datasheet 4.2 56-ball vf bga package for 64- and 128-mbit density (0.75 mm ball pitch) note: address a22 is only valid on 128-mbit density; otherwise, it is a no connect (nc). figure 7. 56-ball vf bga package 0.75 mm ball pitch (for 64- and 128-mb densities only) vfbga 7x8 bottom view - ball side up vfbga 7x8 top view - ball side down 23 456 78 1 a8 vss vcc vpen a18 a6 a4 a9 a20 clk rst# a17 a5 a3 a10 a21 we# a19 a7 a2 a14 wait a16 d12 wp# a22 d15 d6 d4 d2 d1 ce# a0 d14 d13 d11 d10 d9 d0 oe# adv# a1 vssq vcc d3 vccq d8 vssq a11 a12 a13 a15 vccq vss d7 d5 a b c d e f g 2 3 4 5 6 7 81 a8 vss vcc vpen a18 a6 a4 a9 a20 clk rst# a17 a5 a3 a10 a21 we# a19 a7 a2 a14 wait a16 d12 wp# a22 d15 d6 d4 d2 d1 ce# a0 d14 d13 d11 d10 d9 d0 oe# adv# a1 vssq vcc d3 vccq d8 vssq a11 a12 a13 a15 vccq vss d7 d5 a b c d e f g
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 19 4.3 79-ball vf bga for 256-mbit density package figure 8. 79-ball vf bga package for 256-mbit density vfbga top view - ball side down a b c d e 2345 67 8 1 a8 vss vcc vpen a18 a6 a4 a9 a20 clk rst# a17 a5 a3 a10 a21 we# a19 a7 a2 a14 wait a16d12wp#a22 d15 d6 d4 d2 d1 ce# a0 d14 d13 d11 d10 d9 d0 oe# a1 vssq vcc d3 vccq d8 vssq a11 a12 a13 a15 vccq vss d7 d5 9 rfu rfu rfu a23 rfu rfu rfu 10 11 du du du du du du du du du du du du f g du du du du 12 13 adv# vfbga bottom view - ball side up a b c d e 2 3 4 5 6 7 81 a8 vss vcc vpen a18 a6 a4 a9 a20 clk rst# a17 a5 a3 a10 a21 we# a19 a7 a2 a14 wait a16 d12 wp# a22 d15 d6 d4 d2 d1 ce# a0 d14 d13 d11 d10 d9 d0 oe# a1 vssq vcc d3 vccq d8 vssq a11 a12 a13 a15 vccq vss d7 d5 9 rfu rfu rfu a23 rfu rfu rfu 10 11 du du du du du du du du du du du du f g du du du du 12 13 adv#
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 20 datasheet 4.4 signal descriptions table 4 describes the active signals used. table 4. signal descriptions sym type name and function a[a max :a min ] input address: device address. address internally latched during read/write operations. see nomenclature section 1.2 for a max and a min values. d[15:0] input/ output data i/o: inputs data and commands during write operations, outputs data during read operations. float when ce# or oe# are de-asserted. data is internally latched during write operations. ce# input chip enable: active-low; ce#-low selects the device. ce#-high deselects the device, places it in standby mode, and places data and wait outputs in a high-z state. oe# input output enable: active-low; oe#-low enables the device?s output data drivers during read cycles. oe#-high places the data outputs in a high-z state. we# input write enable: active-low; we# controls writes to the flash device. address and data are latched on the rising edge of we#. rst# input reset: active-low; resets internal circuitry and inhibits write operations. this provides data protection during power transitions. rst#-high enables normal operation. exit from reset places the device in asynchronous read-array mode. wp# input write protect: active-low; wp#-low enables the lock-down mechanism. blocks locked down cannot be unlocked with the unlock command. wp#-high overrides the lock-down function enabling blocks to be erased or programmed through software. adv# input address valid: active-low; during synchronous read operations, addresses are latched on the rising edge of adv# or on the rising (or falling) edge of clk, whichever occurs first. vpen input erase/program/block lock enable: controls device protection. when v pen v penlk , flash contents are protected against program and erase. clk input clock: synchronizes the device to the system?s bus frequency in synchronous-read mode, and increments the internal address generator. during synchronous read operations, addresses are latched on adv#?s rising edge or clk?s rising (or falling) edge, whichever occurs first. connect this signal to vcc if the device will not be used in synchronous-read mode. sts open drain output status: indicates the status of the internal state machine. when configured in level mode (default mode), it acts as a ry/by# pin. when configured in one of its pulse modes, it can indicate program and/or erase completion. for alternate configurations of the status pin, see the configuration commands. sts is to be tied to v ccq with a pull-up resistor. wait output wait: indicates invalid data in synchronous-read (burst) modes. wait is high-z whenever ce# is de-asserted. wait is not gated by oe#. vcc power core power supply: core (logic) source voltage. writes to the flash array are inhibited when v cc v lko . device operation at invalid v cc voltages should not be attempted. vccq power i/o power supply: i/o output-driver source voltage. vss power ground: ground reference for device core power supply. connect to system ground. vssq power i/o ground: i/o ground reference for device i/o power supply. connect to system ground. du ? do not use: do not use this ball. this ball should not be connected to any power supplies, signals or other balls and must be left floating. nc ? no connect: no internal connection; can be driven or floated. rfu ? reserved for future use: balls designated as rfu are reserved by intel for future device functionality and enhancement.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 21 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings the absolute maximum ratings are shown in table 5 . warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. 5.2 operating conditions table 5. absolute maximum ratings parameter maximum rating notes temperature under bias ?40 c to +85 c storage temperature ?65 c to +125 c voltage on any signal (except vcc and vccq) ?0.5 v to v ccq +0.5 v 1,2 vcc1 (k3) voltage ?0.2 v to +4.1 v 1 vcc2 (k18) voltage -0.2 v to +3.8 v vccq1 (k3) voltage ?0.2 v to +4.1 v 1 vccq2 (k18) voltage ?0.2 v to +2.45 v 1 output short circuit current 100 ma 3 notes: 1. specified voltages are with respect to v ss . minimum dc voltage is ?0.5 v on input/output signals and ?0.2 v on v cc and v ccq . during transitions, this level may undershoot to ?2.0 v for periods <20 ns. maximum dc voltage on v cc is v cc +0.5 v, which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. maximum dc voltage on input/output signals and v ccq is v ccq +0.5 v, which, during transitions, may overshoot to v ccq +2.0 v for periods <20 ns. 2. program/erase voltage is normally 2.7 v?3.6 v. 3. output shorted for no more than one second. no more than one output shorted at a time. symbol parameter min max units t a operating temperature ?40 +85 c v cc1 core voltage (k3) 2.70 3.60 v v cc2 core voltage (k18) 2.70 3.30 v v ccq1 vccq i/o supply voltage (k3) 2.375 3.60 v v ccq2 vccq i/o supply voltage (k18) 1.65 1.95 v block erase cycles all blocks, v cc = 3 v 100,000 cycles
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 22 datasheet 6.0 electrical specifications 6.1 dc current characteristics table 6. dc current characteristics v cc 2.7 v ? 3.3 v 2.7 v ? 3.6 v v ccq 1.65 v? 1.95 v 2.375 v ? 3.6 v sym parameter notes typ max typ max unit test condition i li input load current 1 1 1 a v cc = v ccmax , v ccq = v ccqmax, v in = v ccq or gnd i lo output leakage current 1 10 10 a v cc = v ccmax , v ccq = v ccqmax, v in = v ccq or gnd i ccs v cc standby 64 mbit, 128 mbit 1, 2, 3, 4 30 55 30 55 a cmos inputs, v cc = v ccmax , v ccq = v ccqmax , device is disabled rst# = v ccq 0.2v/gnd 0.2v 256 mbit 45 80 45 80 a i ccr average v cc read current single word read 1, 3, 4, 5 10 73 10 78 ma v cc = v ccmax , t acc = t avqv asynchronous page mode 16 28 18 30 ma 8 word read t acc = t avqv , t apa = 25 ns, v cc = v ccmax synchronous burst 24 38 32 46 ma burst length = 8 f = 66 mhz(k3), 50 mhz(k18) v cc = v ccmax ce# = v il , oe# = v ih , inputs = v ih or v il 28 40 36 48 ma burst length = 16 i ccw v cc program current 1, 4, 6, 7 50 80 40 70 ma cmos inputs, v pen = v cc i cce v cc block erase current 1, 4, 6, 7 50 80 40 70 ma cmos inputs, v pen = v cc i ccws , i cces v cc program suspend or block erase suspend current 1, 4, 6, 7 20 10 ma device is enabled notes: 1. all currents are rms unless noted. typical values at v cc = 3 v, t a = +25c, best-case address pattern. maximum values at v cc = 3.6 v, worst-case address pattern. 2. includes sts. 3. cmos inputs/outputs are either v cc 0.2 v or v ss 0.2 v. 4. current values are specified over a specific temperature range (?40 c to +85 c). 5. sampled, not 100% tested. 6. i cces, i ccws are specified with device deselected. if device is read while in erase suspend/program suspend, current is i cces plus i ccr or i ccws plus i ccr . 7. v pen < v penlk inhibits block erase, program and lock-bit operations. don?t use v pen outside its valid ranges.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 23 table 7. dc voltage characteristics v cc 2.7 v ? 3.3 v 2.7 v ? 3.6 v v ccq 1.65 v ? 1.95 v 2.375 v ? 3.6 v sym parameter (1) note min max min max unit test condition v il input low voltage cmos 7 0 0.4 0 0.4 v v ih input high voltage cmos 7 v ccq ?0.4 v ccq 2.3 v ccq v v ol output low voltage cmos 2, 4 0.2 0.2 v v cc = v ccmin , v ccq = v ccqmin, i oh = 100 a v oh output high voltage cmos 2, 4 v ccq ?0.2 v ccq ?0.2 v v cc = v ccmin , v ccq = v ccqmin, i oh = ?100 a v penlk v pen lock-out during normal operations 3, 5 1.0 1.0 v v penh v pen during block erase, program or lock- bit operations 3, 5 1.65 1.95 2.7 3.6 v v lko v cc lockout voltage 3, 6 1.8 1.8 v v ccqlko v ccq lockout voltage 3 1.0 1.0 v notes: 1. all currents are rms unless noted. typical values at typical v cc , t a = +25c. 2. includes sts. 3. sampled, not 100% tested. 4. i cces, i ccws are specified with device deselected. if device is read while in erase suspend/program suspend, current is i cces plus i ccr or i ccws plus i ccr . 5. v pen < v penlk inhibits block erase, program and lock-bit operations. don?t use v pen outside its valid ranges. 6. block erases, programming and lock-bit configurations are inhibited when v cc 28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 24 datasheet 7.0 ac characteristics 7.1 read operations table 8. ac read characteristics (sheet 1 of 2) vcc 2.7 v - 3.3 v 2.7 v - 3.6 v vccq 1.65 v - 1.95v 2.375 v - 3.6 v num sym parameter (3) density note min max min max unit asynchronous specifications r1 t avav read cycle time 64 mbit 110 110 ns 128 mbit 115 115 ns 256 mbit 120 120 ns r2 t avqv address to output delay 64 mbit 6 110 110 ns 128 mbit 115 115 ns 256 mbit 120 120 ns r3 t elqv ce# low to output delay 64 mbit 3 110 110 ns 128 mbit 115 115 ns 256 mbit 120 120 ns r4 t glqv oe# low to output delay 3 30 25 ns r5 t phqv rst# high to output delay 64 mbit 190 180 ns 128 mbit 220 210 ns 256 mbit 220 210 ns r6 t elqx ce# low to output in low-z 0 0 ns r7 t glqx oe# low to output in low-z 3 0 0 ns r8 t ehqz ce# high to output in high-z 5 25 25 ns r9 t ghqz oe# high to output in high-z 5 25 25 ns r10 t oh output hold from first occurring address, ce# or oe# change 50 0 ns r11 t ehel ce# high to ce# low 1 0 0 ns r12 t eltl/h ce# low to wait low 30 25 ns r13 t ehtz ce# high to wait high-z 30 25 ns latching specifications r101 t avvh address setup to adv# high 9 7 ns r102 t elvh ce# low to adv# high 9 7 ns r103 t vlqv adv# low to output delay 64 mbit 110 110 ns 128 mbit 115 115 ns 256 mbit 120 120 ns
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 25 r104 t vlvh adv# pulse width low 12 10 ns r105 t vhvl adv# pulse width high 12 10 ns r106 t vhax address hold from adv# high 410 8 ns r108 t apa page address access 6 30 25 ns clock specifications r200 f clk clk frequency 50 66 mhz r201 t clk clk period 7 20 15 ns r202 t ch/l clk high/low time 7 7 4.5 ns r203 t chcl clk fall/rise time 7 3 3 ns synchronous specifications r301 t avch address valid setup to clk 9 7 ns r302 t vlch adv# low setup to clk 9 7 ns r303 t elch ce# low setup to clk 9 7 ns r304 t chqv clk to output delay 7 15 13 ns r305 t chqx output hold from clk 3 3 ns r306 t chax address hold from clk 4 10 8 ns r307 t chtl/h clk to wait delay 7, 8 15 13 ns r312 t chvl clk to adv# low 3 3 ns notes: 1. ce# high between synchronous reads = 15 ns. data bus read voltage is v ccq1 . 2. see figure 17, ?ac input/output reference waveform? on page 32 for timing measurements and maximum allowable input slew rate. 3. oe# may be delayed up to t elqv -t glqv after ce# low without impact on t elqv . 4. address hold in synchronous burst-mode is t chax or t vhax , whichever timing specification is satisfied first. 5. sampled, not 100% tested. 6. for devices configured to standard word read mode, r108(t apa ) will equal r2(t avqv ). 7. the clock duty cycle should be 50% (approx.). 8. applies only to subsequent synchronous reads. table 8. ac read characteristics (sheet 2 of 2) vcc 2.7 v - 3.3 v 2.7 v - 3.6 v vccq 1.65 v - 1.95v 2.375 v - 3.6 v num sym parameter (3) density note min max min max unit
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 26 datasheet figure 9. single word asynchronous read waveform figure 10. page mode read waveform r5 r10 r7 r6 r13 r9 r4 r8 r3 r1 r2 r1 a ddress [a] adv# ce# [e} oe# [g] wait [t] data [d/q] rst# [p] q0 q1 q6 q7 r108 r108 r7 r6 r13 r9 r4 r8 r3 r105 r105 r2 a[max:3] [a] a[2:0] adv# [v] ce# [e] oe# [g] wait [t] data [d/q]
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 27 note: wait (shown active low) can be configured to assert either during, or one clock before, valid data. figure 11. single word burst read waveform latency count r305 r304 r4 r13 r307 r12 r9 r7 r8 r303 r102 r3 r104 r106 r101 r104 r105 r105 r2 r306 r301 clk [ c] address [a] adv# [v] ce # [ e] oe # [ g] wait [t] data [d/q]
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 28 datasheet notes: 1. section 4.9.13, ?first access latency count (cr.11-13)? on page 38 describes how to insert clock cycles during the initial access. 2. wait (shown active high) can be configured to assert either during or one clock before valid data. figure 12. 8 word synchronous burst read waveform latency co note 1 q0 q1 q6 q7 r304 r304 r7 r6 r13 r12 r9 r4 r8 r3 r106 r101 r105 r105 r1 r1 r2 r305 r305 r305 r304 clk address [a] adv# ce# [e] oe# [g] wait [t] data [d/q] figure 13. clock input ac waveform clk [c] v ih v il r203 r202 r201 clkinput.wmf
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 29 7.2 write operation table 9. write characteristics vcc 2.7 - 3.3 v 2.7 - 3.6 v vccq 1.65 - 1.95 v 2.375 - 3.6 v num sym parameter (1) density notes min min unit w1 t phwl rst# high recovery to we# low 64 mbit 190 180 ns 128 mbit 220 210 ns 256 mbit 2 220 210 ns w2 t elwl ce# setup to we# low 0 0 ns w3 t wlwh we# write pulse width low 3 60 60 ns w4 t dvwh data setup to we# high 60 60 ns w5 t avwh address setup to we# high 55 55 ns w6 t wheh ce# hold from we# high 0 0 ns w7 t whdx data hold from we# high 0 0 ns w8 t whax address hold from we# high 0 0 ns w9 t whwl we# pulse width high 4, 5 35 30 ns w10 t vpwh (t vpeh ) v pen setup to we# (ce#) going high 00ns w11 t qvvl v pen hold from valid srd, sts going high 3, 7 0 0 w12 t qvbl wp# hold from status read 2, 3, 6 0 0 ns w13 t bhwh wp# setup to we# high 2 200 200 ns w14 t whgl write recovery before read 35 35 ns w16 t whqv we# high to data valid 2 t avqv +40 t avqv +40 ns notes: 1. read timing characteristics during block erase, program and lock-bit operations are the same as during read-only operations. refer to ac characteristics - read-only operations. 2. a write operation can be initiated or terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t whwl ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). hence, t whwl = t ehel = t whel = t ehwl . 6. for array access, t avqv is required in addition to t whgl for any accesses after a write. 7. sts timings are based on sts configured in its ry/by# default mode.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 30 datasheet figure 14. write to write waveform figure 15. asynchronous read to write waveform w1 w7 w4 w7 w4 w3 w9 w3 w9 w3 w3 w6 w2 w6 w2 w8 w8 w5 w5 address [a] ce# [e} we# [w] oe# [g] data [d/q] rst #/ rp# [p] q d r5 w7 w4 r10 r7 r6 w6 w3 w3 w2 r9 r4 r8 r3 w8 w5 r1 r2 r1 a ddress [a] ce# [e} oe# [g] we# [w] data [d/q] rst# [p]
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 31 7.3 block erase and program operation performance figure 16. asynchronous write to read waveform table 10. block erase and program operation performance # sym parameter notes min typ max unit w0 t whqv1 , t ehqv1 write buffer program time (time to program 64 bytes/32 words) 4, 5, 6 320 960 s t whqv2 , t ehqv2 word program time (using word program command) 4 150 450 s t whqv3 , t ehqv3 block program time (using write-to- buffer command) 4 0.7 2.1 sec t bbwb buffered-efp buffer write time 1, 3, 4 288 864 s t bwb buffered-efp block write time 1, 3, 4 0.58 1.7 sec t befp-setup buffered-efp set-up time 1, 3, 4 n/a 5.0 s t whqv4 , t ehqv4 block erase time 4 1.0 4.0 sec t whrh1 , t ehrh1 program suspend latency time to read 20 25 s t whrh , t ehrh erase suspend latency time to read 20 25 s wy t sts sts pulse width low time 4 250 ns notes: 1. typical values measured at t a = +25 c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. these performance numbers are valid for all speed versions. 3. sampled but not 100% tested. 4. excludes system level overhead. 5. these values are valid when the buffer is full, and the start address is aligned on 32-bit boundary. 6. effective word program time (t whqv1 , t ehqv1 ) is 10.0 s/word (typ). d q w1 r9 r8 r4 r3 r2 w7 w4 w1 4 w18 w3 w3 r10 w6 w2 r1 r1 w8 w5 a ddress [a] ce# [e} we# [w] oe# [g] data [d/q] rst# [p]
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 32 datasheet 7.4 ac test conditions note: ac test inputs are driven at v ccq for logic ?1? and 0.0 v for logic ?0.? input/output timing begins or ends at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed occurs at v cc = v ccmin . note: c l included jig capacitance. 7.5 capacitance figure 17. ac input/output reference waveform io_ref.wmf input v ccq /2 v ccq /2 output v ccq 0v test points figure 18. transient equivalent testing load circuit device under test r 2 r 1 v ccq out c l load_ckt.wmf table 11. test configuration component value for worst case speed conditions test configuration c l (pf) r 1 r 2 v ccqmin standard test 30 25k 25k note: c l includes jig capacitance. table 12. capacitance sym parameter (1) typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v notes: 1. t a = +25c, f = 1 mhz. 2. sampled, not 100% tested.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 33 8.0 power and reset this section provides an overview of some system level considerations in regards to the flash device. this section provides a brief description of power-up, power-down, decoupling and reset design considerations. 8.1 power-up/down characteristics in order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up and power-down v cc and v ccq together. it is also recommended to power-up v pen with or slightly after v cc . conversely, v pen must power down with or slightly before v cc . 8.2 power supply decoupling when the device is enabled, many internal conditions change. circuits are energized, charge pumps are switched on, and internal voltage nodes are ramped. all of this internal activities produce transient signals. the magnitude of the transient signals depends on the device and system loading. to minimize the effect of these transient signals, a 0.1 f ceramic capacitor is required across each v cc /v ss and v ccq /v ssq signal . capacitors should be placed as close as possible to device connections. additionally, for every eight flash devices, a 4.7 f electrolytic capacitor should be placed between v cc and v ss at the power supply connection. this 4.7 f capacitor should help overcome voltage slumps caused by pcb (print circuit board) trace inductance. 8.3 reset characteristics by holding the flash device in reset during power-up and power-down transitions, invalid bus conditions may be masked. the flash device enters reset mode when rst# is driven low. in reset, internal flash circuitry is disabled and outputs are placed in a high-impedance state. after return from reset, a certain amount of time is required before the flash device is able to perform normal operations. after return from reset, the flash device defaults to asynchronous page mode. if rst# is driven low during a program or erase operation, the program or erase operation will be aborted and the memory contents at the aborted block or address are no longer valid. see figure 19, ?reset operation waveforms? on page 34 for detailed information regarding reset timings.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 34 datasheet 8.4 reset operation figure 19. reset operation waveforms table 13. reset specifications num symbol parameter notes min max unit p1 t plph rst# pulse width low 1,2,3,4 100 ns p2 t plrh rst# low to device reset during erase 1,3,4,7 20 s rst# low to device reset during program 1,3,4,7 10 p3 t vccph v cc power valid to rst# de-assertion (high) 1,4,5,6 60 notes: 1. these specifications are valid for all product versions (packages and speeds). 2. the device may reset if t plph is 28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 35 9.0 bus operations this section provides an overview of device bus operations. the on-chip write state machine (wsm) manages all block-erase and word-program algorithms. the system cpu provides control of all in-system read, write, and erase operations of the device via the system bus. device commands are written to the command user interface (cui) to control all of the flash memory device?s operations. the cui does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled. 9.1 bus operations overview bus cycles to and from the device conform to standard microprocessor bus operations. table 14 summarizes the bus operations and the voltage levels that must be applied to the device control signals when operating within each device mode. whenever ce# is asserted, the device is in an active state; it is selected and its internal circuits are active. oe# and we# determine whether d[15:0] are outputs or inputs, respectively. 9.1.1 read mode to perform a bus read operation, ce# and oe# must be asserted. ce# is the device-select control; when active, it enables the flash memory device. oe# is the data-output control; when active, the addressed flash memory data is driven onto the i/o bus. for all read states, we# and rst# must be de-asserted. see section 7.1, ?read operations? on page 24 . refer to section 10.0, ?read modes? on page 39 for details on reading from the flash array, and refer to section 14.0, ?special modes? on page 56 for details regarding all other available read states. table 14. bus operations mode rst# ce# oe# (1) we# (1) adv# wait v pen data sts (default mode) notes synch array read v ih enabled v il v ih xvalidx d out high-z asynch. reads and synch. status, query and identifier reads v ih enabled v il v ih x driven x d out high-z 2 output disable v ih enabled v ih v ih x driven x high-z high-z standby v ih disabled x x x high-z x high-z high-z reset v il x x x x high-z x high-z high-z cui command write v ih enabled v ih v il x driven x d in high-z array writes v ih enabled v ih v il x driven v penh d in v il 3, 4 notes: 1. oe# and we# should never be asserted simultaneously, but if done, oe# overrides we#. 2. refer to dc characteristics. when v pen v penlk , memory contents can be read but not altered. 3. x should be v il or v ih for the control pins and v penlk or v penh for v pen . for outputs, x should be v ol or v oh . 4. array writes are either program or erase operations.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 36 datasheet 9.1.2 write/program to perform a bus write operation, both ce# and we# are asserted, and oe# is de-asserted. all device write operations are asynchronous, with clk being ignored. during a write operation, address and data are latched on the rising edge of we# or ce#, whichever occurs first. see table 15, ?command bus definitions? on page 37 for bus cycle commands. see section 7.2, ?write operation? on page 29 . write operations with invalid v cc and/or v pen voltages can produce spurious results and should not be attempted. 9.1.3 output disable when oe# is de-asserted, device outputs, d[ 15:0], are disabled and placed in a high - impedance state. 9.1.4 standby when ce# is de-asserted, the device is deselected and placed in standby, substantially reducing power consumption. in standby, the data outputs are placed in a high-impedance state independent of the level placed on oe#. if the device is de-selected (ce# de-asserted) during a program or erase operation, it will continue to consume active power until the program or erase operation is completed. there is no additional latency for subsequent read operations. 9.1.5 reset after initial power-up or reset, the device defaults to read array mode and the device status register is set to 0x80. if already in read array mode, asserting rst# de-energizes all internal circuits, and places the output drivers in a high - impedance state. after returning from reset (rst# de-asserted) a minimum amount of time is required before the initial read access outputs valid data. also, a minimum delay is required after a reset before a write cycle can be initiated. after this wake - up interval has passed, normal operation is restored. see section 7.1, ?read operations? on page 24 for reset timing details. note: if rst# is asserted during a program or erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may have been only partially written or erased. when rst# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. when rst# has been de-asserted, the device will be reset to read array mode. if the system is returning from an aborted program or erase operation, a minimum amount of time must be satisfied before a read or write operation is initiated. as with any automated device, it is important to assert rst# when the system is reset. when the system comes out of reset, the system processor will attempt to read from the flash memory if it is the system boot device. automated flash memories provide status information when read during program or block erase operations. if a cpu reset occurs with no flash memory reset, improper cpu initialization may occur because the flash memory may be providing status information rather than array data. intel ? flash memory devices allow proper cpu initialization following a system reset through the use of the rst# input. rst# should be controlled by the same low-true reset signal that resets the system cpu.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 37 9.2 device commands device operations are initiated by writing specific device commands to the command user interface (cui). (see table 15 .) table 15. command bus definitions (sheet 1 of 2) command bus cycles first bus cycle second bus cycle type addr data type addr data read read array 1 write any address 0xff read address of memory to be read array data read identifier 2 write any address 0x90 read identifier code address identifier code data read query (cfi) 2 write any address 0x98 read query code address query code data read status register 2write address within block 0x70 read address with block status register data clear status register 1 write any address 0x50 program program 2 write address of memory location to be programed 0x40 or 0x10 write address of memory to be programed data to be programed write to buffer 4 number of buffer words + 3 write address within block 0xe8 write address within block number of words to be written to buffer buffered efp 2write address of memory location to be programed 0x80 write address within block 0xd0 erase block erase 2 write address within block 0x20 write address within block 0xd0 suspend erase/program suspend 1 write any address 0xb0 resume erase/program resume 1 write any address 0xd0
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 38 datasheet register configuration (burst, lock, sts and protection) read configuration register 2 write cd 1 0x60 write cd 1 0x03 lock block 2 write address within block 0x60 write address within block 0x01 unlock block 2 write address within block 0x60 write address within block 0xd0 lock-down block 2 write address within block 0x60 write address within block 0x2f sts 2 write any address 0xb8 write any address cc 2 protection program 2write pa 5 0xc0 write pa 5 data to be programmed to the protection register lock protection program 2write lock protection address for 128- bit 0xc0 write lock protection address for 128-bit 0xfffd lock 2k otp protection 2write lock protection address for 2k-bit 0xc0 write lpa1 lpd 3 notes: 1. cd = configuration register data presented on device addresses a[a min +15:a min ]. a[a max :a min +16] address bits must be cleared . see table 16, ?read configuration register? on page 40 for rcr bit descriptions. 2. cc = sts configuration code on d[7:0]. 3. lpd = lock protection register1 data. valid values are between 0xfffe and 0x0000. 4. the second cycle of the write-to-buffer command is the count of words to load into the buffer, followed by data streaming up to the count value. then a confirm command (0xd0) is issued to execute the program operation. refer to figure 25, ?write to buffer flowchart? on page 70 . 5. pa = valid protection register address. table 15. command bus definitions (sheet 2 of 2) command bus cycles first bus cycle second bus cycle type addr data type addr data
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 39 10.0 read modes the device supports four types of read modes: read array, read identifier, read status or read query. upon power-up or return from reset, the device defaults to read array mode. to change the device?s read mode, the appropriate read command must be written to the device. (see section 9.2, ?device commands? on page 37 .) see section 14.0, ?special modes? on page 56 for details regarding read status, read id, and cfi query modes. the device supports two types of array read modes: asynchronous page mode and synchronous burst mode. asynchronous page mode is the default read mode after powered-up, or after a reset. the rcr must be configured to enable synchronous burst reads of the flash memory array. (see section 10.3, ?read configuration register? on page 40 .) the read array command functions independent of v pen . the following sections describes read- array mode operations in detail. 10.1 asynchronous page-mode read asynchronous page mode is the default read mode upon power-up or return from reset. however, to perform array reads after any other device operation (e.g., a write operation), the read array command must be issued in order to read from the flash memory. asynchronous page-mode reads are permitted in all blocks, and it is used to access device register information. note: asynchronous page mode reads can only be performed when rcr bit 15 is set (default). (see section 10.3, ?read configuration register? on page 40 .) to perform an asynchronous page-mode read, an address is driven onto a[a max :a min ], and ce# and oe# are asserted. we# and rst# must be de-asserted. adv# must be held low throughout the read cycle. clk and wait are not used for asynchronous page-mode reads. if only asynchronous reads are to be performed, it is recommended that clk be tied to a valid v ih level. array data is driven out on d[15:0] after a minimum delay. (see section 7.1, ?read operations? on page 24 .) in asynchronous page mode, one of 16 eight-word groups are ?sensed? simultaneously from the flash memory and loaded into an internal page buffer. after the initial access delay, the first word out of the data buffer corresponds to the initial address, a[a max :a min ]. address bits a[a max :a min + 3] are latched by the device. however, the lower address bits, a[a min +2:a min ], are not latched. address bits a[a min +2:a min ] determine which word of the eight-word group is output from the data buffer at any given time. subsequent reads from the device come from the page buffer, and are output on d[15:0] after a minimum delay, as long as address bits a[a min +2:a min ] are the only address bits that change. data can be read from the page buffer multiple times, and in any order. if address bits a[a max :a min +3] change at any time, or if ce# is toggled, the device will sense and load a new eight-word group from the flash memory into the page buffer. by controlling certain signals, such as ce# and/or oe#, the device can be made to output less than eight-words of data. asynchronous page-mode read is used to access register information, but only one word is loaded into the page buffer.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 40 datasheet 10.2 synchronous burst-mode read since asynchronous page mode is the default read mode following a device power-up or reset, the appropriate bits in the rcr must be set before synchronous burst mode reads of the flash memory can occur. see section 10.3, ?read configuration register? on page 40 for details. immediately after configuring the rcr, it is not necessary to issue the read array command (0xff) before performing a synchronous burst-mode read. however, to perform a synchronous burst-mode read after executing any other device operation (e.g., a write operation), it is necessary to issue the read array command before performing a synchronous burst-mode read of the flash memory. to perform a synchronous burst-mode read, an address is driven onto a[a max :a min ], and ce# and oe# are asserted. we# and rst# must be de-asserted. adv# is asserted, then de-asserted to latch the address. alternatively, adv# can remain asserted throughout the burst access, in which case, the address is latched on the next valid clk edge. in synchronous burst mode, one or two of the 16 eight-word groups are ?sensed? simultaneously from the flash memory and loaded into an internal page buffer. after the initial access delay, the first word is output from the data buffer on the next valid clk edge. subsequent buffer data is output on valid clk edges. synchronous burst-mode reads can only step through the data buffer once, and can only do so in a sequential manner; starting from the address latched at the beginning of the burst cycle (see section 7.1, ?read operations? on page 24 ). the device supports 8- or 16- word bursts. however, by controlling certain control signals, such as ce# and/or oe#, the device can output less than 8/16-words of synchronous data. a burst-mode read can be used to access register information. wh en a burst-mode read is performed on a register, only one word is loaded into the data buffer. in burst mode, the address is latched by either the rising edge of adv# or the next valid edge of clk with adv# low, whichever occurs first. 10.3 read configuration register the read configuration register (rcr) is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. to modify the rcr settings, write the rcr command to the device (see section 9.0, ?bus operations? on page 35 ). rcr contents can be examined by writing the read identifier command to the device. see section 14.2, ?read device identifier? on page 57 ). the rcr register is shown in table 16 . the following sections describe ea ch rcr bit in detail. il. table 16. read configuration register (sheet 1 of 2) read configuration register (rcr) default value = 0xffc7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read mode latency count wait polarity data hold wait delay burst seq clk edge res res res burst length rm lc[3:0] wp dh wd bs ce r r r bl[2:0] bit name description 15 read mode (rm) 0 = synchronous burst-mode read 1 = asynchronous page-mode read (default)
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 41 10.3.1 read mode the read mode (rm) bit selects synchronous burst mode or asynchronous page mode operation of the device. when the rm bit is set, asynchronous page mode is selected (default). when rm is cleared, synchronous burst mode is selected. synchronous burst mode is used for array reads, whereas asynchronous page mode is used for reading array data, status register information, device id information, and cfi information. note that when operating in synchronous burst mode, status, id, and cfi information will be driven onto the bus on the next valid clock edge following the initial synchronous access delay, and will remain on the bus for the duration of the access cycle. 10.3.2 latency count the latency count bits, lc[3:0], tell the device how many clock cycles must elapse from the rising edge of adv# (or from the first valid clock edge after adv# is asserted) until the first data word is to be driven onto d[15:0]. table 20 on page 42 shows the data output latency for the valid settings of lc[3:0]. see table 17 on page 42 for latency setting values matched for input clock frequencies. 14:11 latency count (lc[3:0]) 0000 = code 0. rfu 0001 = code 1. rfu 0010 =code 2 0011 =code 3 0100 =code 4 0101 =code 5 0110 = code 6 0111 = code 7 1000 = code 8 1001 = code 9 1010 = code 10 1011 - 1111 = code 11 - code 15. all these codes are rfu 10 wait polarity (wp) 0 = wait signal is active low 1 = wait signal is active high (default) 9 data hold (dh) 0 = hold data for one clock 1 = hold data for two clocks (default) 8 wait delay (wd) 0 = wait de-asserted with valid data 1 = wait de-asserted one clock before valid data (default) 7 burst sequence (bs) 0 = reserved 1 = linear (default) 6 clock edge (ce) 0 = falling edge 1 = rising edge (default) 5:3 reserved (r) 000 - cannot be changed 2:0 burst length (bl[2:0]) 001 = rfu 010 = 8-word burst 011 = 16-word burst 111 = rfu (default) table 16. read configuration register (sheet 2 of 2)
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 42 datasheet figure 20. first-access latency count code 1 (reserved code 6 code 5 code 4 code 3 code 2 code 0 (reserved) code 7 valid address valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output address [a] adv# [v] dq 15-0 [d/q] clk [c] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] table 17. latency count table lc setting 64 mb 128 mb 256 mb k18 k3 k18 k3 k18 k3 2 1 to 21 mhz 1 to 20 mhz 1 to 20 mhz 1 to 19 mhz 1 to 19 mhz 1 to 18 mhz 3 22 to 31 mhz 21 to 30 mhz 21 to 30 mhz 20 to 29 mhz 20 to 28 mhz 19 to 28 mhz 4 32 to 42 mhz 31 to 41 mhz 31 to 40 mhz 30 to 39 mhz 29 to 38 mhz 29 to 37 mhz 5 43 to 50 mhz 42 to 51 mhz 41 to 50 mhz 40 to 49 mhz 39 to 47 mhz 38 to 46 mhz 6 na 51 to 61 mhz na 50 to 59 mhz 48 to 50 mhz 47 to 56 mhz 7 na 62 to 66 mhz na 59 to 66 mhz na 57 to 66 mhz
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 43 figure 21 shows an example of a lc setting of code 3. 10.3.3 wait polarity the wait polarity (wp) bit selects the asserted, or true, state of wait. when wp is set, wait is an active-high signal (default). when wp is cleared, wait is an active-low signal. 10.3.4 data hold for burst read operations, the data hold (dh) bit determines whether the data output remains valid on d[15:0] for one or two clock cycles. when dh is set, output data is held for two clocks (default). when dh is cleared, output data is held for one clock cycle. (see figure 22 .) the processor?s data setup time and the flash memory?s clock-to-data output delay should be considered in determining whether to hold output data for one or two clocks. figure 21. example latency count setting clk ce# adv# a[max:0] d[15:0] t data code 3 address data 012 34 r103 high-z figure 22. data hold timing dq 15-0 [d/q] clk [c] valid output valid output valid output dq 15-0 [d/q] valid output valid output 1 clk data hold 2 clk data hold
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 44 datasheet 10.3.5 wait delay the wait delay (wd) bit controls the wait signal?s delay behavior during synchronous burst reads. wait can be asserted either during, or one clock cycle before, valid data is output on d[15:0].when wd is set, wait is de-asserted one clock before valid data (default). when wd is cleared, wait is de-asserted with valid data. the setting of wd is dependent on the system and cpu data sampling requirements. 10.3.6 burst sequence the burst sequence (br) bit selects linear-burst sequence (default). only linear-burst sequence is supported. table 18 shows the synchronous burst sequence for all burst lengths. 10.3.7 clock edge the clock edge (ce) bit selects either a rising (default) or falling clock edge for clk. this is the clock edge that is used at the start of a burst cycle to output synchronous data and to assert/de- assert wait. 10.3.8 burst length bl[2:0] selects the linear burst length for all synchronous burst reads of the flash memory. the burst length can be configured to be an 8-word or a 16-word burst. once a burst cycle begins, the device will output synchronous burst data until it reaches the end of the burstable address space. table 18. burst sequence word ordering start addr. (dec) burst addressing sequence (dec) 8-word burst (bl[2:0] = 010) 16-word burst (bl[2:0] = 011) 0 0-1-2-3-4-5-6-7 0-1-2-3-4?14-15 1 1-2-3-4-5-6-7-0 1-2-3-4-5?15-0 2 2-3-4-5-6-7-0-1 2-3-4-5-6?0-1 3 3-4-5-6-7-0-1-2 3-4-5-6-7?1-2 4 4-5-6-7-0-1-2-3 4-5-6-7-8?2-3 5 5-6-7-0-1-2-3-4 5-6-7-8-9?3-4 6 6-7-0-1-2-3-4-5 6-7-8-9-10?4-5 7 7-0-1-2-3-4-5-6 7-8-9-10-11?5-6 ? ? ? 14 14-15-0-1-2?12-13 15 15-0-1-2-3?13-14 ? ? ?
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 45 11.0 program modes the device supports three different programming methods: word programming, write-buffer programming, and buffered enhanced factory programming or buffered-efp. successful programming requires the addressed block to be unlocked. if the block is locked down, wp# must be de-asserted and the block unlocked before attempting to program the array. an attempt to program a locked block will result in the operation aborting, and sr[1] and sr[4] being set, indicating a programming error. the following sections describe device programming in detail. 11.1 word programming word programming is performed by executing the word program command. word programming is a non-buffered operation and programs one word to the flash array based on the initial program address a[a max :a min ]. to determine the status of a word-program operation, poll the status register and analyze the bits. if the flash device is put in standby mode during a program operation, the device will continue to program the word until the operation is complete; then the device will enter standby mode. refer to figure 26, ?word programming flowchart? on page 71 for a detailed flow on how to implement a word program operation. during programming, the write state machine executes a sequence of internally-timed events that program the desired data bits and verifies that the bits are sufficiently programmed. programming the flash memory array changes ?ones? to ?zeros.? memory array bits that are zeros can be changed to ones only by erasing the block. when programming has finished, status register bit sr4 set indicates a programming failure. if sr3 is set, this indicates that the write state machine could not perform the word programming operation because v pen was outside of its acceptable limits. if sr1 is set, the word programming operation had attempted to program a locked block, causing the operation to abort. after examining the status register, it should be cleared using the clear status register command before issuing a new command. any valid command can follow, after word programming has completed. 11.2 write-buffer programming the device features a 32-word write buffer to allow optimum programming performance. for write-buffer programming, data is first written to an on-chip write buffer, then programmed into the flash memory array in buffer-size increments. optimal performance is realized when programming is buffer-size aligned to the 32-word write-buffer boundary. the write-buffer is directly mapped to the flash array through a[a min +4:a min ]. unaligned buffered writes will decrease program performance. buffered writes can improve system programming performance more than 20x over non write-buffer programming. to perform write-buffer programming, the write-to-buffer setup command, 0xe8, is issued along with the block address (see section 9.2, ?device commands? on page 37 ). status register information is updated, and a read from the block address will return status register data showing the write buffer?s availability. note: do not issue the read status register command during this sequence. sr7 indicates the availability of the write buffer for loading data. if sr7 is set, the write
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 46 datasheet buffer is available; if not set, the write buffer is not available. to retry, issue the write-to-buffer setup command again, and re-check sr7. when sr7 is set, the write buffer is available. see figure 25, ?write to buffer flowchart? on page 70 . next, a word count (actual word count - 1) is written to the device at the buffer address. this tells the device how many data words will be written to the write buffer, up to the maximum size of the write buffer. the valid range of values for word count is 0x00 to 0x1f. on the next write, a device start address is given along with the first data to be written to the flash memory array. subsequent writes provide additional device addresses and data. all data addresses must lie within the start address plus the word count. maximum programming performance and lower power are obtained by aligning the starting address at the beginning of a 32 word boundary. a misaligned starting address will result in a doubling of the total program time. after the last data is written to the write buffer, the write-to-buffer confirm command is issued. the write state machine begins to copy the write buffer contents to the flash memory array. if a command other than the write-to-buffer confirm command is written to the device, a command sequence error will occur and status register bits sr4, sr5 and sr7 will be set. if an error occurs while writing to the array, the device will stop programming, and status register bit sr4 and sr7 will be set, indicating a programming failure. additional buffer writes can be initiated by issuing another write-to-buffer setup command and repeating the write-to-buffer sequence. anytime sr4 and sr5 are set, the device will not accept write-to-buffer commands. if an attempt is made to program past a block boundary using the write-to-buffer command, the device will abort the operation. this will generate a command sequence error, and status register bits sr4 and sr5 will be set. if write-buffer programming is attempted while v pen is below v penlk , status register bits sr3 and sr4 will be set. if any errors are detected that have set status register bits, the status register should be cleared using the clear status register command. 11.3 program suspend to execute a program suspend, execute the program suspend command. a suspend operation halts any in - progress programming operation. the suspend command can be written to any device address. a suspend command allows data to be accessed from any memory location other than those suspended. a program operation can be suspended to perform a device read. a program operation nested within an erase suspend operation can be suspended to read the flash device. once the program process starts, a suspend operation can only occur at certain points in the program algorithm. erase suspend operations cannot resume until program operations initiated during the erase suspend are complete. all device read functions are permitted during a suspend operation. during a suspend, v pen must remain at a valid program level and wp# must not change. also, a minimum amount of time is required between issuing a program or erase command and then issuing a suspend command.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 47 11.4 program resume to resume (i.e., continue) a program suspend operation, execute the program resume command. the resume command can be written to any device address. when a program operation is nested within an erase suspend operation and the program suspend command is issued, the device will suspend the program operation. when the resume command is issued, the device will resume and complete the program operation. once the nested program operation is completed, an additional resume command is required to complete the block erase operation. the device supports a maximum suspend/resume of two nested routines. see figure 27, ?program suspend/resume flowchart? on page 72 . 11.5 buffered enhanced factory programming (buffered-efp) buffered-efp speeds up mlc flash programming for today?s beat-rate-sensitive manufacturing environments. this enhanced algorithm eliminates traditional elements that drive up overhead in off-board or on-board, off-line or in-line, manual or automated programmer systems. buffered-efp is different than non-buffered efp mode; it incorporates a write buffer to spread mlc program performance across 32 data words. additionally, verification occurs in the same phase as programming, an inherent requirement of two-bi t-per-cell technology to accurately program the correct state. a single two-cycle command sequence programs an entire block of data. this enhancement eliminates three write cycles per buffer page, two commands and the word count per each set of 32 data words. host programmer bus cycles fill the device write buffer, followed by a status check of sr.0 to determine when the data from that page has completed programming into sequential flash memory locations. following the buffer-to-flash programming sequence, the wsm increments internal addressing to automatically select the next 32-word array boundary. this aspect of buffered-efp saves programming equipment address-bus setup overhead. in combination, these enhancements allow programming equipment to stream data to the device. with proper continuity testing, programming equipment can rely on the wsm internal verification to assure the device has programmed properly. this capability eliminates the external post-program verification and its associated overhead. buffered-efp consists of three phases: setup, program/ verify, and exit. refer to figure 28, ?buffered enhanced factory programming procedure flowchart? on page 73 for a graphical representation of buffered-efp. 11.5.1 buffered-efp requirements and considerations buffered-efp requirements: ? ambient temperature: t a = 25 c 5 c ? v cc within specified operating range ? v pen driven to v penh ? target block unlocked before issuing the setup and confirm commands ? wa 0 (first word address in block to be programmed) must be held constant from setup phase through all data streaming in the target block, until transition to the exit phase is desired ? wa 0 must align with the start of an array buffer boundary 1
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 48 datasheet buffered-efp considerations: ? for optimum performance, limit cycling below 100 erase cycles per block 2 ? buffered-efp programs one block at a time, all buffer data must fall within a single block 3 ? buffered-efp cannot be suspended ? programming to flash can only occur when the buffer is full 4 1 buffer boundary in array is determined by a[ a min +4:a min ] (00h through 1fh). alignment start point is a[ a min +4:a min ]=0. 2 some degradation in performance may occur if this limit is exceeded, but the internal algorithm will continue to work properly. 3 if the internal address counter increments beyond th e block?s maximum address, addressing will wrap around to the beginning of the block. 4 if the number of words is less than 32, as in the case of the last page program sequence for a block, remaining locations must be filled with ffffh. the responsibility to manage this falls within the programming equipment, not the customer data file. see figure 28, ?buffered enhanced factory programming procedure flowchart? on page 73 , for a detailed flowchart of the buffered-efp operation. 11.5.2 buffered-efp setup phase after receiving the buffered-efp setup (80h) and confirm (d0h) command sequence, device sr.7 transitions from a ?1? to a ?0,? indicating that the wsm is busy with the buffered-efp algorithm startup. a delay before checking sr.7 is required to allow the wsm time to perform all of its setups and checks (block lock status and v pen level). if an error is detected, sr.4 is set and buffered-efp operation terminates. if the block was found locked, sr.1 is also set. sr.3 is set if the error occurred due to the v pen level being incorrect. 11.5.3 buffered-efp program and verify phase after setup completion, the host programming system must check sr.0 to determine ?data-stream ready? status. sr.0=0 indicates that the buffered-efp program/verify phase is activated and the write buffer is available. two basic sequences repeat in this phase: loading the write buffer, followed by buffer data programming to the array. for buffered-efp, the count value for buffer loading is always the maximum buffer size of 32 words. during the page loading sequence, data received is stored to sequential buffer locations starting at address 00h. programming of that page to the flash array starts immediately when the buffer is full. warning: the buffer must be completely full for programming to occur. supplying an address outside the current block?s range during a buffer fill sequence will cause the operation to lockup. note: if the number of words is less than 32, as in the case of the last page program sequence for a block, remaining locations must be filled with ffffh. the responsibility to manage this falls within the programming equipment, not the customer data file. data words from the write buffer are directed to sequential memory locations in the array, programming takes up where the last page sequence left off. the host programming system must poll sr.0 to determine when the page program sequence completes. sr.0=0 indicates that all
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 49 buffer data has been transferred to the flash array, sr.0=1 indicates that the wsm is still busy. the host system may check full status for errors at any time, but it is only necessary on a block basis, after buffered-efp exit. the host programming system continues the buffered-efp algorithm by providing the next set of data words to the buffer. alternatively, it can terminate this phase by changing the block address.the program/verify phase concludes when the interfacing programmer writes to a different block address; data supplied must be ffffh. upon program/verify phase completion, the device enters the buffered-efp exit phase. 11.5.4 buffered-efp exit phase sr.7=1 indicates that the device has returned to normal operating conditions. a full status check should be performed at this time to ensure the entire block programmed successfully. after buffered-efp exit, any valid cui command can be issued. the buffered-efp sr.7 and sr.0 truth table is shown in table 19 . . table 19. buffered-efp sr.7 and sr.0 truth table sr.7 sr.0 condition 0 0 device is busy, buffer is available. 0 1 device is busy, buffer is not available. 1 0 device is ready, buffer is available. 1 1 invalid state.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 50 datasheet 12.0 erase mode flash erasing is performed on a block basis; therefore, only one block can be erased at a time. when a block is erased, all bits within that block will read as a logic level one. to determine the status of a block erase, poll the status register and analyze the bits. the following section describes block erase operations in detail. 12.1 block erase block erase operations are initiated by writing the block erase command to the address of the block to be erased (refer to section 9.2, ?device commands? on page 37 ). this is followed by the block erase confirm command written to the address of the block to be erased. if the device is placed in standby (ce# de-asserted) during an erase operation, the device will continue to erase the block until the erase operation is completed before entering standby. v pen must be above v penlk and the block must be unlocked (see figure 29, ?block erase flowchart? on page 74 ). also, v pen must remain at a valid level, and wp# must remain unchanged while in erase suspend. during a block erase, the write state machine executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block are erased. erasing the flash memory changes array data from ?zeros? to ?ones.? status register bit sr7 indicates block erase status while the sequence executes. if status register bit sr5 is set after erase completion, this indicates an erase failure. if sr3 is set, this indicates that the write state machine could not perform the erase operation because v pen was outside of its acceptable limits. if sr1 is set, the erase operation attempted to erase a locked block, causing the operation to abort. ce# or oe# must be toggled to update status register contents. after examining the status register, it should be cleared using the clear status register command before issuing a new command. any valid command can follow, once the block erase operation has completed. 12.2 erase suspend issuing the erase suspend command while erasing suspends the block erase operation. this allows data to be accessed from memory locations other than the one being erased. the erase suspend command can be issued to any device address within the block. a block erase operation can be suspended to perform either a word program or a read operation within any block, except the block that is in an erase suspend state (see figure 30, ?erase suspend/resume flowchart? on page 75 ). when a block erase operation is executing, issuing the erase suspend command requests the write state machine to suspend the erase algorithm at predetermined points. an erase operation cannot be nested within another erase suspend operation. block erase is suspended when status register bits sr[7,6] are set. suspend latency is specified in section 7.3, ?block erase and program operation performance? on page 31 . block erase cannot resume until program operations initiated during erase suspend complete. read array, read status register, read identifier, cfi query, and program resume are valid commands during erase suspend. additionally, clear status register, program, program suspend, erase resume, block lock, block unlock, and block lock-down are valid commands during erase suspend.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 51 12.3 erase resume to resume (i.e., continue) an erase suspend operation, execute the erase resume command. the resume command can be written to any device address. when a program operation is nested within an erase suspend operation and the program suspend command is issued, the device will suspend the program operation. when the resume command is issued, the device will resume the program operations first. once the nested program operation is completed, an additional resume command is required to complete the block erase operation. the device supports a maximum suspend/resume of two nested routines. see figure 29, ?block erase flowchart? on page 74 .
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 52 datasheet 13.0 security modes this device offers both hardware and software security features. block lock operations, the protection registers, and vpen enable the user to implement various levels of data protection. the following section describes security features in detail. 13.1 block locking operations individual instant block locking is used to protect user code and/or data within the flash memory array. all blocks power up locked to protect array data from being altered during power transitions. any block can be locked or unlocked without latency. locked blocks cannot be programmed or erased; they can only be read. software-controlled security is implemented with the block lock and block unlock commands. hardware-controlled security can be implemented with the block lock-down command and wp#. refer to figure 23 for a state diagram of the flash security features. also see figure 32, ?block lock operations flowchart? on page 77 . figure 23. block locking state diagram [x00] [x01] power-up/reset unlocked locked [011] [111] [110] locked- down 4,5 software locked [011] hardware locked 5 unlocked wp# hardware control notes: 1. [a,b,c] represents [wp#, d1, d0]. x = don?t care. 2. d1 indicates block lock-down status. d1 = ?0?, lock-down has not been issued to this block. d1 = ?1?, lock-down has been issued to this block. 3. d0 indicates block lock status. d0 = ?0?, block is unlocked. d0 = ?1?, block is locked. 4. locked-down = hardware + software locked. 5. [011] states should be tracked by system software to determine difference between hardware locked and locked-down states. software block lock (0x60/0x01) or software block unlock (0x60/0xd0) software block lock-down (0x60/0x2f) wp# hardware control
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 53 13.1.1 block lock all blocks default to the locked state after initial power-up or reset. an unlocked block can be locked by issuing the block lock command sequence. this sets the block lock status bit and fully protects the block from program or erase. attempted program or erase operations to a locked block will return an error in sr1. 13.1.2 block unlock a locked block can be unlocked by issuing the block unlock command. all unlocked blocks return to the locked state when the device is reset or powered-down. unlocked blocks may be programmed or erased. 13.1.3 block lock-down the lock-down block command adds an additional level of security to the device. issuing the lock-down block command sets the lock-down status bit and locks the block. the lock-down block command can be used if the block?s current state is either locked or unlocked. once this bit is set, wp# is enabled as a hardware lock control for that particular block. if a block is locked- down and wp# is de-asserted, the user may issue the unlock block command to allow program or erase operations on that block. note: only device reset or power-down can clear the lock-down status bit. 13.1.4 block lock during erase suspend blocks may be locked, unlocked, or locked down during an erase suspend operation. first, write the erase suspend command to the device. after checking sr7 and sr6 to determine that the erase operation has suspended, write the desired lock command sequence to a block. the lock status bit(s) will change immediately. if the block being locked or locked-down is the same block that is suspended, the lock status bit(s) will still change immediately, but the erase operation will complete when resumed. after completing lock, unlock, read, or program operations, resume the erase operation with the erase resume command. note: a block lock setup command followed by any command other than block lock, block unlock, or block lock-down will produce a command sequence error and set status register bits sr4 and sr5. if this error occurs while an erase is suspended, sr4 and sr5 will remain set after the erase operation is resumed unless the status register is cleared first using the clear status register command. otherwise, possible erase errors may become masked by the command sequence error. locking operations cannot occur during program suspend. appendix a, ?write state machine (wsm)? on page 59 shows valid commands during erase suspend. 13.1.5 wp# lock-down control if the lock-down status bit is set for a particular block, the wp# signal is then enabled as a master lock/unlock override for that particular block. when wp# is asserted, all blocks that have the lock- down status bit set are automatically put into the lock-down state and cannot be unlocked with the unlock block command. once wp# is de-asserted, the block reverts back to a locked state; only then can it be unlocked via software.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 54 datasheet 13.2 protection registers the device includes 17 128-bit protection registers, pr16 through pr0, which can be used to increase system security or to provide identification capabilities. pr0[63:0] are permanently programmed by intel with a unique number for each flash device. pr0[127:64] and pr1 through pr16 are one-time programmable (otp) and available for the customer to program. once programmed, the user-programmable registers can be locked to prevent further programming. note: user-programmable bits are otp and may be programed individually. however, once the protection register is locked, the entire user segment is locked and no more user bits may be programmed. figure 24. protection register memory map 0x89 pr lock register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x102 0x109 0x8a 0x91 0x84 0x88 0x85 0x81 0x80 pr lock register 0 user-programmable intel factory-programmed (user-programmable) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (user-programmable) pr16 pr1 pr0
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 55 13.2.1 reading the protection registers to read protection register data, issue the read identifier command along with the address corresponding to the desired word of register data. (see figure 24 on page 54 .) protection register data is read 16 bits at a time. 13.2.2 programming the protection registers to program a protection register, issue the protection program command, plus a desired protection register offset. see figure 24 on page 54 for appropriate address offsets of the protection register. only one word may be programmed to the user segment at a time. issuing the protection program command outside the register?s address space results in a status register error (sr4=1). 13.2.3 locking the protection registers to lock a protection register, program the corresponding bit in the pr lock register by issuing the program pr lock register command followed by the desired pr lock register data. bit 0 of pr lock register 0 is already programmed at the intel factory and locks pr0[63:0]. bit 1 of pr lock register 0 can be programmed by the user to lock the user-programmable portion of protection register 0, namely pr0[128:64]. the rest of the bits in pr lock register 0 are not used. pr lock register 1 controls the locking of the remaining 128-bit protection registers. each of the 16 bits of pr lock register 1 corresponds to one of the 16 128-bit protection registers. for example, to lock pr6, program bit 5 in pr lock register 1. after pr lock register bit 1 is programmed (locked), the user segment of the protection register cannot be changed. protection program commands written to a locked section result in a status register error (sr[5:4]=0b11). 13.3 array protection the v pen signal is a hardware mechanism to prohibit array alteration. when the v pen voltage is below the v penlk voltage, array contents cannot be altered. to ensure a proper erase or program operation, v pen must be set to a valid voltage level. to determine the status of an erase or program operation, poll the status register and analyze the bits.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 56 datasheet 14.0 special modes this section describes in details how to read the status, id and cfi registers. this sections also details how to configure the sts signal. 14.1 read status register the status of the device can be determined by reading the status register. to read the status register, issue the read status register command. status register data is automatically made available following a word program, block erase, or block lock command sequence. subsequent reads from the device after any of these command sequences will output that the device?s status until another valid command is written to the device (e.g. read array). the status register is read using single asynchr onous- and single synchronous-reads only; page- or burst-mode reads cannot be used to read the status register. status register data is output on d[7:0], while 0x00 is output on d[15:8]. the falling edge of oe# or ce# (which ever occurs first) updates and latches the status register contents. the ready bit (sr7) provides overall status of the device. status register bits sr[6:1] present status and error information about the program, erase, suspend, v pen , and block-locked operation. care should be taken to avoid status register ambiguity when issuing valid 2-cycle commands during erase suspend. if a command sequence error occurs during an erase-suspend state, the status register will contain the command sequence error status (sr[7,5:4] set). when the erase operation resumes and finishes, possible errors du ring the erase operation cannot be detected via the status register because it will contain the previous error status. to avoid this situation, always clear the status register prior to resuming erase operations. table 20. status register description (sheet 1 of 2) status register (sr) default value =0x80 ready erase suspend erase error program error vpen program suspend block- locked error buffered-efp status rdy es ee peveps le ps 7654321 0 bit name description 7 ready (rdy) 0 = device is busy; program or erase cycle in progress; sr[0] valid. 1 = device is ready; sr[6:1] are valid. 6 erase suspend (es) 0 = erase suspend not in effect. 1 = erase suspend in effect. 5 erase error (ee) 0 = erase successful. 1 = erase fail or program sequence error when set with sr[7,4]. 4 program error (pe) 0 = program successful. 1 = program fail or program sequence error when set with sr[7,5] 3v pen error (ve) 0 = vpen within acceptable limits during program or erase operation. 1 = vpen < vpenlk during program or erase operation.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 57 14.1.1 clear status register the clear status register command clears the status register and functions independent of v pen . the write state machine sets and clears status bits (sr[7:6,2,0]), but it only sets error bits (sr[5:4,3,1]). the status register should be cleared before starting a command sequence to avoid any ambiguity. a device reset also clears the status register. 14.2 read device identifier the read device identifier command instructs the device to output manufacturer/ device identifier codes, block-lock status, protection register data, and configuration register data when read. (see section 9.2, ?device commands? on page 37 for details on issuing the read device identifier command.) 2 program suspend 0 = program suspend not in effect. 1 = program suspend in effect. 1 block-locked error (le) 0 = block not locked during program or erase. 1 = block locked during program or erase; operation aborted. 0 buffered-efp status (ps) after buffered-efp data is loaded into the buffer: 0 = buffered-efp complete. 1 = buffered-efp in progress. table 20. status register description (sheet 2 of 2) status register (sr) default value =0x80 table 21. device identifier codes item address data (1) manufacturer code 0x0 0x89 k3 64 mb device code 0x1 0x8801 k3 128 mb device code 0x1 0x8802 k3 256 mb device code 0x1 0x8803 k18 64 mb device code 0x1 0x8805 k18 128 mb device code 0x1 0x8806 k18 256 mb device code 0x1 0x8807 block is unlocked block address + 0x2 dq 0 = 0 block is locked dq 0 = 1 block is not locked-down dq 1 = 0 block is locked-down dq 1 = 1 configuration register 0x5 configuration register content protection register lock 0x80 protection register lock 2k-otp lock 0x89 otp lock protection register 0x81 - 0x88 protection register content 2k otp space 0x8a - 0x109 otp content note: data is always available on d[7:0]. d[15:8] is 0x00.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 58 datasheet 14.3 read query/cfi the query register contains an assortment of flas h product information such as block size, density, allowable command sets, electrical specifications and other product information. the data contained in this register conforms to the common flash interface (cfi) protocol. to obtain any information from the query register, execute the read query register command. see section 9.2, ?device commands? on page 37 for details on issuing the cfi query command. refer to appendix b, ?common flash interface? on page 64 for a detailed explanation of the cfi register. information contained in this register can on ly be accessed by executing a single-word read. 14.4 sts configuration (easy bga package only) to configure the sts signal, execute the configuration command. the sts signal can be configured for level or pulse mode. once configured to a particular mode, it remains in that mode until the device is powered down, reset or another configuration command is issued to change the mode. after power-up or reset, the default configuration is level mode. level mode works similar to a ready/busy signal (ry/by#), indicating the status of the write state machine (wsm) during a program or erase operation. the sts configuration command may only be given when the device is not busy or suspended. the possible sts configurations and usage are described in table 22 . table 22. sts configuration coding definitions dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 reserved pulse on program complete (1) pulse on erase complete (1) dq 1? dq 0 = sts configuration codes notes 00 = default, level mode; device ready indication used to control hold to a memory controller to prevent accessing a flash memory subsystem while any flash device's wsm is busy. 01 = pulse on erase complete used to generate a system interr upt pulse when any flash device in an array has completed a block erase. helpful for reformatting blocks after file system free space reclamation or ?cleanup.? 10 = pulse on program complete used to generate a system interr upt pulse when any flash device in an array has completed a program operation. provides highest performance for servicing continuous buffer write operations. 11 = pulse on erase or program complete used to generate system interrupts to trigger servicing of flash arrays when either erase or program operations are completed, when a common interrupt service routine is desired. notes: 1. when configured in one of the pulse modes, sts pulses low with a typical pulse width of 250 ns. 2. an invalid configuration code will result in both status register bits sr.4 and sr.5 being set.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 59 appendix a write state machine (wsm) a.1 nomenclature note: numbered notes referenced in superscript can be found at the end of the last table. table 23. arrangement of next state table pages next states current states part a / page 1 part b / page 1 part a / page 2 part b / page 2
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 60 datasheet table 24. next state table part a current state sr7 sr0 data when read command input and next state read array 0xff program setup 0x10/ 0x40 write to buffer setup 2,3 0xe8 befp setup 1 0x30 erase setup 0x20 erase/ befp/ unlock confirm 7 0xd0 program/ erase confirm 7 0xd0 program/ erase suspend 5 0xb0 read array 1 0 array read array program setup write to buffer setup befp setup erase setup read array read status read status 1 0 status read array program setup write to buffer setup befp setup erase setup read array read status read config 1 0 config read array program setup write to buffer setup befp setup erase setup read array read status read query 1 0 cfi read array program setup write to buffer setup befp setup erase setup read array read status lock setup 6 10 status botch (command seq.error) if second cycle is anything other than 0xd0, 0x01, 0x2f, or 0x03 lock setup erase susp 6 10 status botch erase susp.(command seq. error) if second cycle is anything other than 0xd0, 0x01, 0x2f, or 0x03 botch (command seq. error) 9 10 status read array program setup botch befp setup erase setup read array read status botch erase susp.(command seq. error) 9 10 status read array ers. susp. program setup ers. susp. botch erase. susp. read status ers. susp. read array ers. susp. read array ers.susp. erase read status ers. susp. botch prog. susp.(command seq. error) 9 10 status read array prog. susp. read array prog. susp. botch prog. susp. read array prog. susp. read array prog. susp. program (busy) read status prog. susp. botch both susp. 8 10 status read array both susp. read array both susp. botch both susp. read array both susp. read array both susp. program (busy) ers. susp. read status both susp. otp/prot. prog. setup 10 status otp/protection register program otp/prot prog. (busy) 0z status otp/protection register program (busy) otp.prot prog. (done) 10 status read array program setup write to buffer setup befp setup erase setup read array read status prog. setup 1 0 status program (busy) prog. setup ers. susp. 10 status program (busy) ers. susp. program (busy) 0 z status program (busy) read status prog. susp. program (busy) ers. susp. 0z status program (busy) ers. susp. read status both susp. read status prog. susp. 10 status read array prog. susp. read array prog. susp. read array prog. susp. program (busy) read status prog. susp. read array prog. susp. 10 array read array prog. susp. read array prog. susp. read array prog. susp. program (busy) read status prog. susp. read config prog. susp. 10 config read array prog. susp. read array prog. susp. read array prog. susp. program (busy) read status prog. susp. read query prog. susp. 10 cfi read array prog. susp. read array prog. susp. read array prog. susp. program (busy) read status prog. susp. program (done) 1 0 status read array program setup write to buffer setup befp setup erase setup read array read status read status both susp. 8 10 status read array both susp. program (busy) ers. susp. read status both susp. read array both susp. 8 10 array read array both susp. program (busy) ers. susp. read status both susp. read config both susp. 8 10 config read array both susp. program (busy) ers. susp. read status both susp. read query both susp. 8 10 cfi read array both susp. program (busy) ers. susp. read status both susp. befp setup 1 0 status botch (command seq. error) befp setup- time botch (command seq. error) befp setup-time 0 1 status if time-out > 5 us, go to befp load; if time-out < 5 us, stay in befp setup-time befp load 0 0 status initialize buffer load count to 31; if buffer count=0, then go to befp (busy); for buffer count>0 and same block addr. stay in befp load; if block addr. changed, go to befp exit
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 61 befp (busy) 0 1 status to exit, change block addr; to continue proceed to befp after sr0=0. befp exit (busy) 0 1 status internally timed; go to befp exit after internal timeout; transition indicated by sr0=0 befp exit 1 0 status read array program setup write to buffer setup befp setup erase setup read array read status write to buffer setup 10 status repeat command until sr7=1. next cycle will be interpre ted as count load. count load 1 0 status word count load (actual number of words-1) . lowest five bits will be assu med as the count. device assumes next cycles will be d ata load. data load 1 0 status data load; to quit or abort, change the bl ock address during a write. the ui will botch on a block change. repeat data load unt il word count is reached, next command must be write to buffer confirm write to buffer confirm 10 status botch (command seq. error) program (busy) botch (command seq. error) write to buffer setup ers. susp. 10 status repeat command unt il sr7=1. next cycle will be interp reted as count load ers. susp.. count load ers. susp. 10 status word count load (actual number of words-1). lowest five bits will be assumed as the count. device assumes next cycles will be d ata load ers. susp.. data load ers. susp. 10 status data load; to quit or abort, change the bl ock address during a write. the ui will botch on a block change. repeat data load unt il word count is reached, next command must be write to buffer confirm ers. susp. write to buffer confirm ers. susp. 10 status botch ers. susp.(command seq. error) program (busy) ers. susp. botch ers. susp.(command seq. error) erase setup 1 0 status botch (command seq. error erase (busy) botch (command seq. error) erase (busy) 0 z status erase (busy) read status ers. susp. 10 status read array ers. susp. program setup ers. susp. write to buffer setup ers. susp. read status ers. susp. read array ers. susp. read array ers. susp. erase (busy) read status ers. susp. read array ers. susp. 10 array read array ers. susp program setup ers. susp. write to buffer setup ers. susp read array ers. susp. read array ers. susp read array ers. susp. erase (busy) read status ers. susp. read config ers. susp. 10 config read array ers. susp program setup ers. susp. write to buffer setup ers. susp read array ers. susp read array ers. susp read array ers. susp. erase (busy) read status ers. susp. read query ers. susp. 10 cfi read array ers. susp program setup ers. susp. write to buffer setup ers. susp read array ers. susp read array ers. susp read array ers. susp. erase (busy) read status ers. susp. erase (done) 1 0 status read array program setup write to buffer setup befp setup erase setup read array read status sts reconfig setup 10 status if second cycle is 0x00 or 0x01 or 0x02 or 0x03, then reconfigure the sts functionality and go to read status; if not bot ch. sts reconfig setup ers. susp. 10 status if second cycle is 0x00 or 0x01 or 0x02 or 0x 03, then reconfigure the sts functionality and go to read status ers. susp; if not botch ers. susp. sts reconfig setup prog. susp. 10 status if second cycle is 0x00 or 0x01 or 0x02 or 0x03, then reconfigur e the sts functionality and go to read status prog.susp; if not botch prog. susp. sts reconfig setup both susp. 10 status if second cycle is 0x00 or 0x01 or 0x02 or 0x03, then reconfigur e the sts functionality and go to read status both susp; if not botch both susp. table 24. next state table part a current state sr7 sr0 data when read command input and next state read array 0xff program setup 0x10/ 0x40 write to buffer setup 2,3 0xe8 befp setup 1 0x30 erase setup 0x20 erase/ befp/ unlock confirm 7 0xd0 program/ erase confirm 7 0xd0 program/ erase suspend 5 0xb0
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 62 datasheet table 25. next state table part b current state sr7 sr0 data when read command input and next state read status 0x70 clear status 4 0x50 read config 0x90 sts re- config 0xb8 read query 0x98 lock setup 0x60 otp/prot program setup 0xc0 illegal commands read array 1 0 array read status read array read config sts reconfig setup read query lock setup otp/prot prog. setup read array read status 1 0 status read status read array read config sts reconfig setup read query lock setup otp/prot prog. setup read array read config 1 0 config read status read array read config sts reconfig setup read query lock setup otp/prot prog. setup read array read query 1 0 cfi read status read array read config sts reconfig setup read query lock setup otp/prot prog. setup read array lock setup 6 10 status botch(command seq.error) if second cycle is anything other than 0xd0, 0x01, 0x2f, or 0x03 lock setup erase susp 6 10 status botch erase susp.(command seq. error) if second cycle is anything other than 0xd0, 0x01, 0x2f, or 0x03 botch (command seq. error) 9 10 status read status read array read config sts reconfig setup read query lock setup otp/prot prog. setup read array botch erase susp.(command seq. error) 9 10 status read status ers. susp. read array ers. susp. read config ers. susp. sts reconfig setup ers.susp. read query ers. susp. lock setup ers. susp. read array ers. susp. read array botch prog. susp.(command seq. error) 9 10 status read status prog. susp. read array prog. susp. read config prog susp. sts reconfig setup prog susp. read query prog. susp. read array prog. susp read array prog susp. botch both susp. 8 10 status read status both susp. read array both susp. read config both susp. sts reconfig setup both susp. read query both susp. read array both susp. read array both susp. otp/prot. prog. setup 10 status otp/protection register program otp/prot register program otp/prot prog. (busy) 0z status otp/protection register program (busy) otp/prot register program (busy) otp.prot prog. (done) 10 status read status read array read config sts reconfig setup read query lock setup otp/prot prog. setup read array prog. setup 1 0 status program (busy) prog. setup ers. susp. 10 status program (busy) ers. susp. program (busy) 0 z status program (busy) program (busy) ers. susp. 0z status program (busy) ers. susp. read status prog. susp. 10 status read status prog. susp. read array prog susp. read config prog. susp. sts reconfig setup prog. susp. read query prog susp. read array prog. susp. read array prog. susp. read array prog. susp. 10 array read status prog. susp. read array prog susp. read config prog. susp. sts reconfig setup prog. susp. read query prog susp. read array prog. susp. read array prog. susp. read config prog. susp. 10 config read status prog. susp. read array prog susp. read config prog. susp. sts reconfig setup prog. susp. read query prog susp. read array prog. susp. read array prog. susp. read query prog. susp. 10 cfi read status prog. susp. read array prog susp. read config prog. susp. sts reconfig setup prog. susp. read query prog susp. read array prog. susp. read array prog. susp. program (done) 1 0 status read status read array read config sts reconfig setup read query lock setup prot. prog. setup read array read status both susp. 8 10 status read status both susp. read array both susp. read config both susp. sts reconfig setup both susp. read query both susp. read array both susp read array both susp. read array both susp. 8 10 array read status both susp. read array both susp. read config both susp. sts reconfig setup both susp. read query both susp. read array both susp read array both susp. read config both susp. 8 10 config read status both susp. read array both susp. read config both susp. sts reconfig setup both susp. read query both susp. read array both susp read array both susp. read query both susp. 8 10 cfi read status both susp. read array both susp. read config both susp. sts reconfig setup both susp. read query both susp. read array both susp read array both susp. befp setup 1 0 status botch (command sequence error) befp setup- time 01 status if time-out> 5us, go to befp load; if time-out<5us, stay in befp setup-time befp load 0 0 status initialize buffer load count to 31; if buffer count=0, then go to befp (busy); for buffer count>0 and same block addr. stay in befp load; if block addr. changed, go to befp exit
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 63 befp (busy) 0 1 status to exit, change block addr; to continue proceed to befp after sr0=0. befp exit (busy) 01 status internally timed; go to befp exit after internal timeout; transition indicated by sr0=0 befp exit 1 0 status read status read array read config sts reconfig setup read query lock setup prot. prog. setup read array write to buffer setup 10 status repeat command until sr7=1. next cycle will be interpreted as count load. count load 1 0 status word count load (actual number of words-1). lowest five bits will be assumed as the count. device assumes next cycles wil l be data load. data load 1 0 status data load; to quit or abort, chang e the block address during a writ e. the ui will bo tch on a block change. repeat data load unt il word count is reached, next command must be write to buffer confirm write to buffer confirm 10 status botch (command sequence error) write to buffer setup ers. susp. 10 status repeat command until sr7=1. next cycle will be interpreted as count load ers. susp.. count load ers. susp. 10 status word count load (actual number of words-1) . lowest five bits will be assu med as the count. device assumes next cycles will be d ata load ers. susp.. data load ers. susp. 10 status data load; to quit or abort, chang e the block address during a writ e. the ui will bo tch on a block change. repeat data load unt il word count is reached, next command must be write to buffer confirm ers. susp. write to buffer confirm ers. susp. 10 status botch ers. susp. (command sequence error) erase setup 1 0 status botch (command sequence error) erase (busy) 0 z status erase (busy) read status ers. susp. 10 status read status ers. susp. read array ers. susp. read config ers. susp. sts reconfig setup ers. susp. read query ers. susp. lock setup ers. susp. read array ers. susp. read array ers. susp. read array ers. susp. 10 array read status ers. susp. read array ers. susp. read config ers. susp. sts reconfig setup ers. susp. read query ers. susp. lock setup ers. susp. read array ers. susp. read array ers. susp. read config ers. susp. 10 config read status ers. susp. read array ers. susp. read config ers. susp. sts reconfig setup ers. susp. read query ers. susp. lock setup ers. susp. read array ers. susp. read array ers. susp. read query ers. susp. 10 cfi read status ers. susp. read array ers. susp. read config ers. susp. sts reconfig setup ers. susp. read query ers. susp. lock setup ers. susp. read array ers. susp. read array ers. susp. erase (done) 1 0 status read status read array read config sts reconfig setup read query lock setup prot. prog. setup read array sts reconfig setup 10 status if second cycle is 0x00 or 0x01 or 0x02 or 0x03, then reconfigure the sts functionality and go to read status; if not bot ch. sts reconfig setup ers. susp. 10 status if second cycle is 0x00 or 0x01 or 0x02 or 0x 03, then reconfigure the sts functionality and go to read status ers. susp; if not botch ers. susp. sts reconfig setup prog. susp. 10 status if second cycle is 0x00 or 0x01 or 0x02 or 0x03, then reconfigure the sts functionality and go to read status prog.susp; if not botch prog. susp. sts reconfig setup both susp. 10 status if second cycle is 0x00 or 0x01 or 0x02 or 0x 03, then reconfigure the sts functionality and go to read status both susp; if not botch both susp. notes: 1. for befp, the block address should be changed only when the buffer is full. 2. start address is the address loaded during the count load cycle. 3. the write to buffer command is invalid when a botch has occurred. the status register should be cleared before issuing the wr ite to buffer command. 4. a clear status register command is allowed during erase or program suspend. 5. when a suspend command is issued while the device is busy (program or erase), the device will not enter suspend until the app ropriate suspend latency has elapsed. any additional commands issued during this latency interval will cause indeterminate results. 6. when the lock/write rcr operation is complete, the device returns to read status mode. if the lock setup command is issued du ring erase suspend, the device will revert to read status ers. susp. 7. the confirm command (0xd0) is interpreted as the second cycle of a two-cycle command while a resume command 0xd0 is interpret ed as a stand-alone, single-cycle command. the device will not resume from suspend when the command sequence 0x20, 0xd0 is issued while in suspend state. 8. both suspend indicates a program suspend nested within an erase suspend. 9. a botch state is indicated when status bits sr4 and sr5 are set, and is the result of an invalid command sequence. the clear status register command (0x50)must be issued to continue. table 25. next state table part b current state sr7 sr0 data when read command input and next state read status 0x70 clear status 4 0x50 read config 0x90 sts re- config 0xb8 read query 0x98 lock setup 0x60 otp/prot program setup 0xc0 illegal commands
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 64 datasheet appendix b common flash interface b.1 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or ?database.? the structure sub-sections and address locations are summarized below. for further details see ap-646 common flash interface (cfi) and command sets (order no 292204) for a full description of cfi. b.2 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). table 26. query structure (1) offset sub-section name description 00000h 0089 manufacturer code 00001h device code (ba+2)h (2) block status register block-specific information 000(04 -0f)h reserved reserved for vendor-specific information 00010h cfi query identification string command set id and vendor data offset 0001bh system interface information device timing & voltage information 00027h device geometry definition flash device layout p (3) primary intel - specific extended query tab le vendor - defined additional information specific to the primary vendor algorithm notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of dev ice bus width and mode. 2. ba = the beginning location of a block address (e.g., 010000h is the beginning location of block 1 when the block size is 64 kword). 3. offset 15 defines ?p? which points to the primary intel - specific extended query table.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 65 b.3 system interface information the following tables give information on the power supplies and the program and erase time details as output by the device when the system software requests system interface information. the values stored are available from an offset address of 1bh. table 27. cfi identification offset length description addr. hex code value 10h 3 query-unique ascii string ?qry? 10 --51 ?q? 11: --52 ?r? 12: --59 ?y? 13h 2 primary vendor command set and control interface id code. 13: --01 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --31 16: --00 17h 2 alternate vendor command set and control interface id code 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 table 28. system interface information offset length description addr. hex code value 1bh 1 v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1b: --27 2.7 v 1ch 1 v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1c: --36 3.6 v 1dh 1 v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1d: --00 0.0 v 1eh 1 v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1e: --00 0.0 v 1fh 1 ?n? such that typical single word program time-out = 2 n s 1f: --08 256 s 20h 1 ?n? such that typical buffer write time-out = 2 n s 20: --09 512 s 21h 1 ?n? such that typical block erase time-out = 2 n ms 21: --0a 1 s 22h 1 ?n? such that typical full chip erase time-out = 2 n ms 22: --00 n/a 23h 1 ?n? such that maximum word program time-out = 2 n times typical 23: --01 512 s 24h 1 ?n? such that maximum buffer write time-out = 2 n times typical 24: --01 1024 s 25h 1 ?n? such that maximum block erase time-out = 2 n times typical 25: --02 4 s 26h 1 ?n? such that maximum chip erase time-out = 2 n times typical 26: --00 na
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 66 datasheet b.4 device geometry definition the following tables give critical details provided by cfi when the software requests flash device geometry information such as the size of the device, types of read interfaces, program buffer size etc., table 29. device geometry definition offset length description address hex value meaning 27h 1 ?n? such that the device size = 2 n in number of bytes 27: see table below 28h 2 flash device interface code assignments: 28: 29: --01 --00 x16 2ah 2 ?n? such that maximum number of bytes in write buffer=2 n 2a: 2b: --06 --00 64 2ch 1 number of erase blocks within the device: 1. x=0 means no erase blocking; the device erases in ?bulk? 2. x specifies the number of device or partition regions with one or more contiguous same- size erase blocks 3. array size = (total blocks) x (individual blocks size) --01 1 2dh 4 erase block region information bits 0-15=y, y+1 = number of identical-size erase blocks bits 16-31=z, region erase block(s) size are z x 256 bytes 2d: see table below 2e: 2f: 00 30: 02 ????x64x32x16x8 15 14 13 12 11 10 9 8 ???????? table 46a. no of erase blocks and erase block region information address 64 mbit 128 mbit 256 mbit) 27 h 17h 18h 19h 2d h 3fh 7fh ffh 2e h 00h 00h 00h
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 67 b.5 primary vendor specific extended query table certain flash features and commands are optional. the primary vendor specific extended query table specifies this and other similar information. table 30. primary vendor specific extended query table offset (1) p=31h length description (optional flash features and commands) add hex code value (p+0)h 3 primary extended query table unique ascii string ?pri? 31: --50 ?p? (p+1)h 32: --52 ?r? (p+2)h 33: --49 ?i? (p+3)h 1 major version number, ascii 34: --31 ?1? (p+4)h 1 minor version number, ascii 35: --31 ?1? (p+5)h (p+6)h (p+7)h (p+8)h 4 optional feature and command support(1=yes, 0=no) bits 11-31 are reserved; undefined bits are ?0?. if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the 30-bit field. bit 0 - chip erase supported bit 1 - suspend erase supported bit 2 -suspend program supported bit 3 - legacy lock/unlock supported bit 4 - queued erase supported bit 5 - instant individual block locking supported bit 6 - protection bits supported bit 7 - page-mode read supported bit 8 - synchronous read supported bit 9 - simultaneous operations supported bit 10 - feature space supported 36: --e6 37: --01 38: --00 39: --00 bit 0 = 0 no bit 1 = 1 yes bit 2 = 1 yes bit3 = 0 no bit 4 = 0 no bit 5= 1 yes bit 6= 1 yes bit 7= 1 yes bit 8 = 1 yes bit 9 = 0 no bit 10 =0 no (p+9)h 1 supported functions after suspend: read array, status, query other supported operations are: bits 1-7 reserved; undefined bits are ?0? bit 0 program supported after erase suspend 3a: --01 01 bit 0=1 yes
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 68 datasheet (p+a)h (p+b)h 2 block status register mask bits 3 -15 are reserved; undefined bits are ?0? bit 0 block lock-bit status register bit active bit 1 block lock down bit status active bit 2 unlock down bit 3b: --07 3c: --00 bit 0 = 1 ye s bit 1 = 1 ye s (p+c)h 1 vcc logic supply highest performance program/ erase voltage bits 0-3 bcd value in 100mv bits 4-7 bcd value in volts 3d: --33 3.3 (p+d)h 1 vpp optimum program/erase supply voltage bits 0-3 bcd value in 100mv bits 4-7 hex value in volts 3e: --00 --0.0v table 31. protection register information offset (1) p=31h length description(optional flash features and commands) add hex code value (p+e)h 1 number of protection register fields in jedec id space. ?00h?, indicates that 256 protection fields are available 3f: --02 02 (p+f)h, (p+10)h, (p+11)h, (p+12)h 4 protection field 1: protection description this field describes user-available one time program- mable(otp) protection register bytes. some are pre- programmed with device-unique serial numbers. others are user-programmable. bits 0-15 point to the protection register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user-program- mable bits 0-7 = lock/bytes jedec-plane physical low address bits 8-15 =lock/bytes jedec-plane physical high address bits 16-23 = ?n? such that 2 n = factory pre-programmed bytes bits 24-31 = ?n? such that 2 n = user-programmable bytes 40: 41: 42: 43: --80 --00 --03 --03 80h 00h 8 bytes 8 bytes (p+13)h, (p+14)h, (p+15)h, (p+16)h, (p+17)h, (p+18)h, (p+19)h, (p+1a)h, (p+1b)h, (p+1c)h 10 protection field 2: protection description bits 0-31 = point to the protection register physical lock- word address in the jedec-plane. following bytes are factory or user-programmable bits 32-39 =?n?-factory pgm?d groups(low byte) bits 40-47=?n?-factory pgm?d groups(high byte) bits 48-55 =?n? such that 2 n =factory programmable bytes per group bits 56-63=?n?-user pgm?d groups(low byte) bits 64-71=?n?-user pgm?d groups(high byte) bits 72-79=?n? such that 2 n = user programmable bytes/ group 44: 45: 46: 47: 48: 49: 4a: 4b: 4c: 4d: --89 --00 --00 --00 --00 --00 --00 --10 --00 --04 89h 00h 00h 00h 0 0 0 16 0 16 note: the variable p is a pointer which is defines at cfi offset 15h. table 30. primary vendor specific extended query table offset (1) p=31h length description (optional flash features and commands) add hex code value
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 69 table 32. burst/page read information offset (1) p=31h length description(optional flash features and commands) add hex code value (p+1d)h 1 page mode read capability bits 0-7=?n? such that 2 n hex value represents the number of read page bytes. see offset 28h for device word width to determine page mode data output width. 00h indicates no read page buffer. 4e: --04 16 bytes (p+1e)h 1 number of synchronous mode read configuration fields that follow. 00h indicates no burst capability 4f: --02 2 (p+1f)h 1 synchronous mode read capability configuration 1 bits 3-7 = reserved bits 0-2 = ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous burst reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts until that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bits 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 50: --02 8 (p+20)h 1 synchronous mode read capability configuration 2 51: --03 16
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 70 datasheet appendix c flowcharts figure 25. write to buffer flowchart start get next target address issue write to buffer command 0xe8 and block address read extended status register (at block address) is buffer available? xsr.7 = full status check if desired programming complete 1. w ord count values on dq 7 -dq 0 are loaded into the count register. count ranges for this device are n = 0x00 to 0x1f. 2. the device outputs the status register when read (xsr is no longer available). 3. write buffer contents will be programmed at the device start address or destination flash address. 4. align the start address on a w rite buffer boundary for maximum programming performance (i.e., a 5 ?a 1 of the start address = 0). 5. the device aborts the w rite to buffer command if the current address is outside the original block address. 6. the status register indicates an "improper command sequence" if the w rite to buffer command is aborted. follow this with a clear status register command. full status check can be done after all erase and write sequences complete. w rite 0xff after the last operation to reset the device to read array mode. 1 = yes device supports buffer writes? set time-out or loop counter time-out or count expired? write confirm 0xd0 and block address another write to buffer? read status register sr.7 = ? 0 1 yes no bus operation standby read command no write write to buffer read standby comments check sr.7 1 = w sm ready 0 = w sm busy status register data transition to v il of either ce# or oe# updates sr addr = block address data = 0xe8 addr = block address xsr.7 = valid addr = block address check xsr.7 1 = w rite buffer available 0 = no w rite buffer available write write confirm data = 0xd0 addr = block address write buffer data, start address x = 0 yes 0 = no no issue read status register command yes use single word programming abort write to buffer? no x = n? write buffer data, block address x = x + 1 write to another block address write to buffer aborted no yes yes write (notes 1, 2) data = n = w ord count n = 0 corresponds to count = 1 addr = block address write (notes 3, 4) data = w rite buffer data addr = start address write word count, block address write (notes 5, 6) data = w rite buffer data addr = block address
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 71 figure 26. word programming flowchart suspend program loop start w rite 0x40, address w rite data and address read status register sr.7 =? full status check if desired program complete full status check procedure repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write 0xff after the last program operation to read array mode. suspend program comments data = 0x40 addr = location to program data = data to program addr = location to program read status register data (see above) v pen range error device protect error program successful sr.3 = sr.1 = 0 0 program error sr.4 = 0 bus operation write write command w ord program setup data status register data. toggle ce# or oe# to update status register data read check sr.7 1 = wsm ready 0 = wsm busy standby 1 1 1 1 0 yes no word program procedure sr.3 must be cleared before further attempts are allowed by the w rite state machine if set during a program attempt sr.4, sr.3 and sr.1 are only cleared by the clear staus register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. comments check sr.3 1 = v pen error detect check sr.1 1 = attempted program to locked block - program aborted check sr.4 1 = data program error bus operation standby standby standby command
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 72 datasheet figure 27. program suspend/resume flowchart start write 0xb0 read status register comments data = 0xb0 addr = x data = 0xff addr = x sr.7 = sr.2 = write 0xff read array data program completed done reading write 0xff write 0xd0 program resumed read array data read array data from block other than the one being programmed. check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = program suspended 0 = program completed data = 0xd0 addr = x bus operation write write read read standby standby write command program suspend read array program resume status register data; toggle ce# or oe# to update status register data addr = x program suspend read array program resume 0 no 0 yes 1 1
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 73 figure 28. buffered enhanced factory programming procedure flowchart sr.0=1=n write data address = wa 0 last data? write ffffh address = other block program done? read status register sr.0=0=y y sr.7=0=n full status check procedure program complete read status register befp exited? sr.7=1=y start write 80h address = wa 0 unlock block write d0h address = wa 0 befp setup done? read status register sr.7=1=n exit n befp program & verify befp exit befp setup check x = 32? initialize count x = 0 increment count x = x+1 y notes: 1. wa 0 = first word address to be programmed within the target block. wa 0 must align on a write buffer boundary. 2. the status register is updated when a system read toggles oe# low-high-low. 3. write buffer contents are programmed sequentially to the flash array starting at wa 0 . the wsm internally increments addressing. n check v pen & lock errors (sr.3, sr.1) sr.7=0=y befp setup comments bus state write (note 1) befp setup write befp confirm read (note 2) standby befp setup done? write unlock block data = 80h address = wa 0 data = d0h address = wa 0 status register address = wa 0 check sr.7 0 = befp ready 1 = befp not ready unlock block standby error condition check if sr.7 = 1: check sr.3, sr.1 sr.3 = 1 = v pen error sr.1 = 1 = locked block befp program & verify comments bus state write (note 3) standby inc. count standby initialize count data = word to program address = wa 0 x = x+1 x = 0 comments bus state standby buffer full? x = 32? if yes, read sr.0 if no, load next data word befp setup time data stream ready? read status register sr.0=0=y sr.0=1=n read standby data stream ready? status register address = wa 0 check sr.0 0 = ready for data 1= not ready for data read buffer full? status register address = wa 0 standby program done? check sr.0 0 = program done 1 = program in progress standby last data? no = fill buffer again yes = exit the program & verify phase write exit program & verify phase x = 32? if yes, read sr.0 if no, load next data word status register address = wa 0 read befp exit check sr.7 0 = exit not completed 1 = exit completed standby repeat for subsequent blocks. after befp exit, a full status check can determine if any program error occurred. see the full status check procedure in the word program flowchart. write ffh to enter read array mode.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 74 datasheet figure 29. block erase flowchart start write 0x20 block address write 0xd0 and block address read status register sr.7 = full status check if desired block erase complete full status check procedure repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. w rite ffh after the last write operation to reset device to read array mode. sr. 1 and 3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.1, 3, 4, 5 are only cleared by the clear staus register command, in cases where multiple blocks are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no suspend erase comments data = 0x20 addr = within block to be erased data = 0xd0 addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy comments check sr.3 1 = v pen low detect check sr.4,5 both 1 = command sequence error read status register data (see above) v pen range error command sequence error block erase successful sr.3 = sr.4,5 = block erase error sr.5 = attempted erase of locked block - aborted sr.1 = status register data toggle ce# or oe# to update status register data check sr.5 1 = block erase error check sr.1 1 = attempted erase of locked block - erase aborted 1 0 0 0 1 1 1 1 0 yes suspend erase loop command erase setup erase confirm bus operation write write standby read command bus operation standby standby standby standby 0
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 75 figure 30. erase suspend/resume flowchart start write 0xb0 read status register comments data = 0xb0 addr =block to suspend (ba) data = read or write addr = write or read address sr.7 = sr.6 = erase completed write 0xff write 0xd0 erase resumed read array data read array or program data from/to block other than the one being erased. check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = erase suspended 0 = erase completed data = 0xd0 addr = suspended block (ba) bus operation write write read or write read standby standby write write 0x70 status register data toggle ce# or oe# to update status register data addr = suspended block (ba) command erase suspend read array or program erase resume 0 0 read or write? done? no read 1 program program loop read array data 1 yes erase suspend/resume procedure
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 76 datasheet figure 31. protection register programming flowchart start write 0xc0 (protection reg. program setup) w rite protect. register address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pen range error protection register programming error locked-register program attempt aborted program successful sr.3, sr.4 = sr.1, sr.4 = sr.1, sr.4 = full status check procedure bus operation write write standby protection program operations can only be addressed within the protection register address space. addresses outside the defined space will return an error. repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. w rite ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases of multiple protection register program operations before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. yes command protection program setup protection program comments data = 0xc0 data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments read status register data toggle ce# or oe# to update status register data standby no 1,1 0,1 1,1 sr.1 sr.3 sr.4 011v pen low 0 0 1 prot. reg. prog. error register 1 0 1 locked: aborted
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 77 figure 32. block lock operations flowchart no optional start write 60h block address write 90h read block lock status locking change? lock change complete write 01,d0,2fh block address write ffh partition address yes write write write (optional) read (optional) standby (optional) write lock setup lock, unlock, or lockdown confirm read id plane block lock status read array data = 60h addr = block to lock/unlock/lock-down (ba) data = 01h (lock block) d0h (unlock block) 2fh (lockdown block) addr = block to lock/unlock/lock-down (ba) data = 90h addr = block address offset +2 (ba+2) block lock status data addr = block address offset +2 (ba+2) confirm locking change on dq 1 , dq 0 . (see block locking state transitions table for valid combinations.) data = ffh addr = block address (ba) bus operation command comments locking operations procedure lock_op.wmf lock confirm lock setup read id plane read array
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 78 datasheet appendix d additional information order number document tool 298636 intel strataflash ? synchronous memory (k3/k18) 256-, 128-, 64-mbit specification update 298136 intel ? persistent storage manager user?s guide 292237 ap-689 using intel ? persistent storage manager 297859 ap-677 intel strataflash ? memory technology 292222 ap-644 designing intel strataflash ? memory into intel ? architecture 292221 ap-663 using the intel strataflash ? memory write buffer 292204 ap-646 common flash interface (cfi) and command sets 292202 ap-644 migration guide to 5 volt intel strataflash ? memory 298161 intel ? flash memory chip scale package user?s guide notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intel?s world wide web home page at http://www.intel.com for technical documentation and tools. 3. for the most current information on intel strataflash memory, visit our website at http:// developer.intel.com/design/flash/isf.
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 datasheet 79 appendix e ordering information rc 28f 128 k access speed (ns) 64 mbit = 110 128 mbit = 115 256 mbit = 120 product family k = 3 volt synchronous intel strataflash ? memory process identifier c = 0.18um 115 18 c voltage identifer (v cc / v ccq ) 3 = 2.7 - 3.6v / 2.375 - 3.6v 18 = 2.7 - 3.6v / 1.65-1.95v density 640 = 64 mbit (8-mb x16) 128 = 128 mbit (16-mb x16) 256 = 256 mbit (32-mb x16) product line designator for all intel ? flash products package designator, extended temperature (-40c to +85c) ge = 0.75 mm vf bga rc = easy bga pc = 64-ball pb-free easy bga table 33. valid combinations density vf bga easy bga lead-free easy bga 64 mbit ge28f640k3c110 ge28f640k18c110 rc28f640k3c110 rc28f640k18c110 not available 128 mbit ge28f128k3c115 ge28f128k18c115 rc28f128k3c115 rc28f128k18c115 pc 28f128k3c115 (144 pc tray) 256 mbit GE28F256K3C120 ge28f256k18c120 rc28f256k3c120 rc28f256k18c120 not available
28f640k3, 28f640k18, 28f128k3, 28f128k18, 28f256k3, 28f256k18 80 datasheet

▲Up To Search▲

Price & Availability of GE28F256K3C120

	To Download GE28F256K3C120 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .